[PATCH] D105390: [X86] Lower insertions into non-0'th 128-bit subvector as broadcast+blend (PR50971)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 356354.
lebedev.ri marked 3 inline comments as done.
lebedev.ri added a comment.

Addressing review notes:

1. Allow i32/i64 for AVX (just pretend they are f32/f64)
2. Only allow YMM vectors, disallow ZMM vectors
3. Disallow i8 even if we can handle it - we have to load mask


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105390/new/

https://reviews.llvm.org/D105390

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/avx-cvt-3.ll
  llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/avx2-masked-gather.ll
  llvm/test/CodeGen/X86/avx512-insert-extract.ll
  llvm/test/CodeGen/X86/insertelement-shuffle.ll
  llvm/test/CodeGen/X86/masked_expandload.ll
  llvm/test/CodeGen/X86/masked_gather.ll
  llvm/test/CodeGen/X86/masked_load.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D105390.356354.patch
Type: text/x-patch
Size: 74113 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210703/aee21087/attachment.bin>