[llvm] f30251f - [GlobalISel] Clean up CombinerHelper::apply* functions to return void.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 2 13:17:14 PDT 2021
Author: Amara Emerson
Date: 2021-07-02T13:17:06-07:00
New Revision: f30251f5272e8b4dc1dec00f01dff807eb8a7895
URL: https://github.com/llvm/llvm-project/commit/f30251f5272e8b4dc1dec00f01dff807eb8a7895
DIFF: https://github.com/llvm/llvm-project/commit/f30251f5272e8b4dc1dec00f01dff807eb8a7895.diff
LOG: [GlobalISel] Clean up CombinerHelper::apply* functions to return void.
For some reason we/I started writing these as returning bool when the return value
is actually ignored by the combiner.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
llvm/include/llvm/Target/GlobalISel/Combine.td
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 6e62ef7dd728..0988fe793176 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -150,11 +150,11 @@ class CombinerHelper {
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
bool matchSextTruncSextLoad(MachineInstr &MI);
- bool applySextTruncSextLoad(MachineInstr &MI);
+ void applySextTruncSextLoad(MachineInstr &MI);
/// Match sext_inreg(load p), imm -> sextload p
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
- bool applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
+ void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
/// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
/// when their source operands are identical.
@@ -239,87 +239,87 @@ class CombinerHelper {
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
- bool applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
+ void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
/// Fold (shift (shift base, x), y) -> (shift base (x+y))
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
- bool applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
+ void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
/// If we have a shift-by-constant of a bitwise logic op that itself has a
/// shift-by-constant operand with identical opcode, we may be able to convert
/// that into 2 independent shifts followed by the logic op.
bool matchShiftOfShiftedLogic(MachineInstr &MI,
ShiftOfShiftedLogic &MatchInfo);
- bool applyShiftOfShiftedLogic(MachineInstr &MI,
+ void applyShiftOfShiftedLogic(MachineInstr &MI,
ShiftOfShiftedLogic &MatchInfo);
/// Transform a multiply by a power-of-2 value to a left shift.
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
- bool applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
+ void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
// Transform a G_SHL with an extended source into a narrower shift if
// possible.
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData);
- bool applyCombineShlOfExtend(MachineInstr &MI,
+ void applyCombineShlOfExtend(MachineInstr &MI,
const RegisterImmPair &MatchData);
/// Reduce a shift by a constant to an unmerge and a shift on a half sized
/// type. This will not produce a shift smaller than \p TargetShiftSize.
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
unsigned &ShiftVal);
- bool applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
+ void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
/// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
bool
matchCombineUnmergeMergeToPlainValues(MachineInstr &MI,
SmallVectorImpl<Register> &Operands);
- bool
+ void
applyCombineUnmergeMergeToPlainValues(MachineInstr &MI,
SmallVectorImpl<Register> &Operands);
/// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
bool matchCombineUnmergeConstant(MachineInstr &MI,
SmallVectorImpl<APInt> &Csts);
- bool applyCombineUnmergeConstant(MachineInstr &MI,
+ void applyCombineUnmergeConstant(MachineInstr &MI,
SmallVectorImpl<APInt> &Csts);
/// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
- bool applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
+ void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
/// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI);
- bool applyCombineUnmergeZExtToZExt(MachineInstr &MI);
+ void applyCombineUnmergeZExtToZExt(MachineInstr &MI);
/// Transform fp_instr(cst) to constant result of the fp operation.
bool matchCombineConstantFoldFpUnary(MachineInstr &MI,
Optional<APFloat> &Cst);
- bool applyCombineConstantFoldFpUnary(MachineInstr &MI,
+ void applyCombineConstantFoldFpUnary(MachineInstr &MI,
Optional<APFloat> &Cst);
/// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg);
- bool applyCombineI2PToP2I(MachineInstr &MI, Register &Reg);
+ void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg);
/// Transform PtrToInt(IntToPtr(x)) to x.
bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg);
- bool applyCombineP2IToI2P(MachineInstr &MI, Register &Reg);
+ void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg);
/// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
/// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
bool matchCombineAddP2IToPtrAdd(MachineInstr &MI,
std::pair<Register, bool> &PtrRegAndCommute);
- bool applyCombineAddP2IToPtrAdd(MachineInstr &MI,
+ void applyCombineAddP2IToPtrAdd(MachineInstr &MI,
std::pair<Register, bool> &PtrRegAndCommute);
// Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
- bool applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
+ void applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
/// Transform anyext(trunc(x)) to x.
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
- bool applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
+ void applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
/// Transform zext(trunc(x)) to x.
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg);
@@ -327,7 +327,7 @@ class CombinerHelper {
/// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
bool matchCombineExtOfExt(MachineInstr &MI,
std::tuple<Register, unsigned> &MatchInfo);
- bool applyCombineExtOfExt(MachineInstr &MI,
+ void applyCombineExtOfExt(MachineInstr &MI,
std::tuple<Register, unsigned> &MatchInfo);
/// Transform fneg(fneg(x)) to x.
@@ -335,23 +335,23 @@ class CombinerHelper {
/// Match fabs(fabs(x)) to fabs(x).
bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src);
- bool applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src);
+ void applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src);
/// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
bool matchCombineTruncOfExt(MachineInstr &MI,
std::pair<Register, unsigned> &MatchInfo);
- bool applyCombineTruncOfExt(MachineInstr &MI,
+ void applyCombineTruncOfExt(MachineInstr &MI,
std::pair<Register, unsigned> &MatchInfo);
/// Transform trunc (shl x, K) to shl (trunc x),
/// K => K < VT.getScalarSizeInBits().
bool matchCombineTruncOfShl(MachineInstr &MI,
std::pair<Register, Register> &MatchInfo);
- bool applyCombineTruncOfShl(MachineInstr &MI,
+ void applyCombineTruncOfShl(MachineInstr &MI,
std::pair<Register, Register> &MatchInfo);
/// Transform G_MUL(x, -1) to G_SUB(0, x)
- bool applyCombineMulByNegativeOne(MachineInstr &MI);
+ void applyCombineMulByNegativeOne(MachineInstr &MI);
/// Return true if any explicit use operand on \p MI is defined by a
/// G_IMPLICIT_DEF.
@@ -418,7 +418,7 @@ class CombinerHelper {
/// Return true if MI is a G_ADD which can be simplified to a G_SUB.
bool matchSimplifyAddToSub(MachineInstr &MI,
std::tuple<Register, Register> &MatchInfo);
- bool applySimplifyAddToSub(MachineInstr &MI,
+ void applySimplifyAddToSub(MachineInstr &MI,
std::tuple<Register, Register> &MatchInfo);
/// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
@@ -427,13 +427,13 @@ class CombinerHelper {
InstructionStepsMatchInfo &MatchInfo);
/// Replace \p MI with a series of instructions described in \p MatchInfo.
- bool applyBuildInstructionSteps(MachineInstr &MI,
+ void applyBuildInstructionSteps(MachineInstr &MI,
InstructionStepsMatchInfo &MatchInfo);
/// Match ashr (shl x, C), C -> sext_inreg (C)
bool matchAshrShlToSextInreg(MachineInstr &MI,
std::tuple<Register, int64_t> &MatchInfo);
- bool applyAshShlToSextInreg(MachineInstr &MI,
+ void applyAshShlToSextInreg(MachineInstr &MI,
std::tuple<Register, int64_t> &MatchInfo);
/// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
@@ -462,27 +462,27 @@ class CombinerHelper {
/// Combine inverting a result of a compare into the opposite cond code.
bool matchNotCmp(MachineInstr &MI, SmallVectorImpl<Register> &RegsToNegate);
- bool applyNotCmp(MachineInstr &MI, SmallVectorImpl<Register> &RegsToNegate);
+ void applyNotCmp(MachineInstr &MI, SmallVectorImpl<Register> &RegsToNegate);
/// Fold (xor (and x, y), y) -> (and (not x), y)
///{
bool matchXorOfAndWithSameReg(MachineInstr &MI,
std::pair<Register, Register> &MatchInfo);
- bool applyXorOfAndWithSameReg(MachineInstr &MI,
+ void applyXorOfAndWithSameReg(MachineInstr &MI,
std::pair<Register, Register> &MatchInfo);
///}
/// Combine G_PTR_ADD with nullptr to G_INTTOPTR
bool matchPtrAddZero(MachineInstr &MI);
- bool applyPtrAddZero(MachineInstr &MI);
+ void applyPtrAddZero(MachineInstr &MI);
/// Combine G_UREM x, (known power of 2) to an add and bitmasking.
- bool applySimplifyURemByPow2(MachineInstr &MI);
+ void applySimplifyURemByPow2(MachineInstr &MI);
bool matchCombineInsertVecElts(MachineInstr &MI,
SmallVectorImpl<Register> &MatchInfo);
- bool applyCombineInsertVecElts(MachineInstr &MI,
+ void applyCombineInsertVecElts(MachineInstr &MI,
SmallVectorImpl<Register> &MatchInfo);
/// Match expression trees of the form
@@ -498,7 +498,7 @@ class CombinerHelper {
std::function<void(MachineIRBuilder &)> &MatchInfo);
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI);
- bool applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI);
+ void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI);
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg);
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg);
@@ -512,11 +512,11 @@ class CombinerHelper {
/// Use a function which takes in a MachineIRBuilder to perform a combine.
/// By default, it erases the instruction \p MI from the function.
- bool applyBuildFn(MachineInstr &MI,
+ void applyBuildFn(MachineInstr &MI,
std::function<void(MachineIRBuilder &)> &MatchInfo);
/// Use a function which takes in a MachineIRBuilder to perform a combine.
/// This variant does not erase \p MI after calling the build function.
- bool applyBuildFnNoErase(MachineInstr &MI,
+ void applyBuildFnNoErase(MachineInstr &MI,
std::function<void(MachineIRBuilder &)> &MatchInfo);
bool matchFunnelShiftToRotate(MachineInstr &MI);
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 678855bd4a11..842a382e4c90 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -142,7 +142,7 @@ def sext_inreg_of_load : GICombineRule<
(defs root:$root, sext_inreg_of_load_matchdata:$matchinfo),
(match (wip_match_opcode G_SEXT_INREG):$root,
[{ return Helper.matchSextInRegOfLoad(*${root}, ${matchinfo}); }]),
- (apply [{ return Helper.applySextInRegOfLoad(*${root}, ${matchinfo}); }])>;
+ (apply [{ Helper.applySextInRegOfLoad(*${root}, ${matchinfo}); }])>;
def combine_indexed_load_store : GICombineRule<
(defs root:$root, indexed_load_store_matchdata:$matchinfo),
@@ -307,7 +307,7 @@ def urem_pow2_to_mask : GICombineRule<
(defs root:$root),
(match (wip_match_opcode G_UREM):$root,
[{ return Helper.matchOperandIsKnownToBeAPowerOfTwo(*${root}, 2); }]),
- (apply [{ return Helper.applySimplifyURemByPow2(*${root}); }])
+ (apply [{ Helper.applySimplifyURemByPow2(*${root}); }])
>;
// Transform d = [su]div(x, y) and r = [su]rem(x, y) - > d, r = [su]divrem(x, y)
@@ -340,7 +340,7 @@ def simplify_add_to_sub: GICombineRule <
(defs root:$root, simplify_add_to_sub_matchinfo:$info),
(match (wip_match_opcode G_ADD):$root,
[{ return Helper.matchSimplifyAddToSub(*${root}, ${info}); }]),
- (apply [{ return Helper.applySimplifyAddToSub(*${root}, ${info});}])
+ (apply [{ Helper.applySimplifyAddToSub(*${root}, ${info});}])
>;
// Fold fp_op(cst) to the constant result of the floating point operation.
@@ -349,7 +349,7 @@ def constant_fp_op: GICombineRule <
(defs root:$root, constant_fp_op_matchinfo:$info),
(match (wip_match_opcode G_FNEG, G_FABS, G_FPTRUNC, G_FSQRT, G_FLOG2):$root,
[{ return Helper.matchCombineConstantFoldFpUnary(*${root}, ${info}); }]),
- (apply [{ return Helper.applyCombineConstantFoldFpUnary(*${root}, ${info}); }])
+ (apply [{ Helper.applyCombineConstantFoldFpUnary(*${root}, ${info}); }])
>;
// Fold int2ptr(ptr2int(x)) -> x
@@ -357,7 +357,7 @@ def p2i_to_i2p: GICombineRule<
(defs root:$root, register_matchinfo:$info),
(match (wip_match_opcode G_INTTOPTR):$root,
[{ return Helper.matchCombineI2PToP2I(*${root}, ${info}); }]),
- (apply [{ return Helper.applyCombineI2PToP2I(*${root}, ${info}); }])
+ (apply [{ Helper.applyCombineI2PToP2I(*${root}, ${info}); }])
>;
// Fold ptr2int(int2ptr(x)) -> x
@@ -365,7 +365,7 @@ def i2p_to_p2i: GICombineRule<
(defs root:$root, register_matchinfo:$info),
(match (wip_match_opcode G_PTRTOINT):$root,
[{ return Helper.matchCombineP2IToI2P(*${root}, ${info}); }]),
- (apply [{ return Helper.applyCombineP2IToI2P(*${root}, ${info}); }])
+ (apply [{ Helper.applyCombineP2IToI2P(*${root}, ${info}); }])
>;
// Fold add ptrtoint(x), y -> ptrtoint (ptr_add x), y
@@ -374,7 +374,7 @@ def add_p2i_to_ptradd : GICombineRule<
(defs root:$root, add_p2i_to_ptradd_matchinfo:$info),
(match (wip_match_opcode G_ADD):$root,
[{ return Helper.matchCombineAddP2IToPtrAdd(*${root}, ${info}); }]),
- (apply [{ return Helper.applyCombineAddP2IToPtrAdd(*${root}, ${info}); }])
+ (apply [{ Helper.applyCombineAddP2IToPtrAdd(*${root}, ${info}); }])
>;
// Fold (ptr_add (int2ptr C1), C2) -> C1 + C2
@@ -383,7 +383,7 @@ def const_ptradd_to_i2p: GICombineRule<
(defs root:$root, const_ptradd_to_i2p_matchinfo:$info),
(match (wip_match_opcode G_PTR_ADD):$root,
[{ return Helper.matchCombineConstPtrAddToI2P(*${root}, ${info}); }]),
- (apply [{ return Helper.applyCombineConstPtrAddToI2P(*${root}, ${info}); }])
+ (apply [{ Helper.applyCombineConstPtrAddToI2P(*${root}, ${info}); }])
>;
// Simplify: (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
@@ -391,7 +391,7 @@ def hoist_logic_op_with_same_opcode_hands: GICombineRule <
(defs root:$root, instruction_steps_matchdata:$info),
(match (wip_match_opcode G_AND, G_OR, G_XOR):$root,
[{ return Helper.matchHoistLogicOpWithSameOpcodeHands(*${root}, ${info}); }]),
- (apply [{ return Helper.applyBuildInstructionSteps(*${root}, ${info});}])
+ (apply [{ Helper.applyBuildInstructionSteps(*${root}, ${info});}])
>;
// Fold ashr (shl x, C), C -> sext_inreg (C)
@@ -400,7 +400,7 @@ def shl_ashr_to_sext_inreg : GICombineRule<
(defs root:$root, shl_ashr_to_sext_inreg_matchinfo:$info),
(match (wip_match_opcode G_ASHR): $root,
[{ return Helper.matchAshrShlToSextInreg(*${root}, ${info}); }]),
- (apply [{ return Helper.applyAshShlToSextInreg(*${root}, ${info});}])
+ (apply [{ Helper.applyAshShlToSextInreg(*${root}, ${info});}])
>;
// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
@@ -408,7 +408,7 @@ def overlapping_and: GICombineRule <
(defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_AND):$root,
[{ return Helper.matchOverlappingAnd(*${root}, ${info}); }]),
- (apply [{ return Helper.applyBuildFn(*${root}, ${info}); }])
+ (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])
>;
// Fold (x & y) -> x or (x & y) -> y when (x & y) is known to equal x or equal y.
@@ -462,7 +462,7 @@ def ext_ext_fold: GICombineRule <
(defs root:$root, ext_ext_fold_matchinfo:$matchinfo),
(match (wip_match_opcode G_ANYEXT, G_SEXT, G_ZEXT):$root,
[{ return Helper.matchCombineExtOfExt(*${root}, ${matchinfo}); }]),
- (apply [{ return Helper.applyCombineExtOfExt(*${root}, ${matchinfo}); }])
+ (apply [{ Helper.applyCombineExtOfExt(*${root}, ${matchinfo}); }])
>;
def not_cmp_fold_matchinfo : GIDefMatchData<"SmallVector<Register, 4>">;
@@ -470,7 +470,7 @@ def not_cmp_fold : GICombineRule<
(defs root:$d, not_cmp_fold_matchinfo:$info),
(match (wip_match_opcode G_XOR): $d,
[{ return Helper.matchNotCmp(*${d}, ${info}); }]),
- (apply [{ return Helper.applyNotCmp(*${d}, ${info}); }])
+ (apply [{ Helper.applyNotCmp(*${d}, ${info}); }])
>;
// Fold (fneg (fneg x)) -> x.
@@ -487,7 +487,7 @@ def unmerge_merge : GICombineRule<
(defs root:$d, unmerge_merge_matchinfo:$info),
(match (wip_match_opcode G_UNMERGE_VALUES): $d,
[{ return Helper.matchCombineUnmergeMergeToPlainValues(*${d}, ${info}); }]),
- (apply [{ return Helper.applyCombineUnmergeMergeToPlainValues(*${d}, ${info}); }])
+ (apply [{ Helper.applyCombineUnmergeMergeToPlainValues(*${d}, ${info}); }])
>;
// Fold (fabs (fabs x)) -> (fabs x).
@@ -504,7 +504,7 @@ def unmerge_cst : GICombineRule<
(defs root:$d, unmerge_cst_matchinfo:$info),
(match (wip_match_opcode G_UNMERGE_VALUES): $d,
[{ return Helper.matchCombineUnmergeConstant(*${d}, ${info}); }]),
- (apply [{ return Helper.applyCombineUnmergeConstant(*${d}, ${info}); }])
+ (apply [{ Helper.applyCombineUnmergeConstant(*${d}, ${info}); }])
>;
// Transform x,y<dead> = unmerge z -> x = trunc z.
@@ -512,7 +512,7 @@ def unmerge_dead_to_trunc : GICombineRule<
(defs root:$d),
(match (wip_match_opcode G_UNMERGE_VALUES): $d,
[{ return Helper.matchCombineUnmergeWithDeadLanesToTrunc(*${d}); }]),
- (apply [{ return Helper.applyCombineUnmergeWithDeadLanesToTrunc(*${d}); }])
+ (apply [{ Helper.applyCombineUnmergeWithDeadLanesToTrunc(*${d}); }])
>;
// Transform x,y = unmerge(zext(z)) -> x = zext z; y = 0.
@@ -520,7 +520,7 @@ def unmerge_zext_to_zext : GICombineRule<
(defs root:$d),
(match (wip_match_opcode G_UNMERGE_VALUES): $d,
[{ return Helper.matchCombineUnmergeZExtToZExt(*${d}); }]),
- (apply [{ return Helper.applyCombineUnmergeZExtToZExt(*${d}); }])
+ (apply [{ Helper.applyCombineUnmergeZExtToZExt(*${d}); }])
>;
// Fold trunc ([asz]ext x) -> x or ([asz]ext x) or (trunc x).
@@ -529,7 +529,7 @@ def trunc_ext_fold: GICombineRule <
(defs root:$root, trunc_ext_fold_matchinfo:$matchinfo),
(match (wip_match_opcode G_TRUNC):$root,
[{ return Helper.matchCombineTruncOfExt(*${root}, ${matchinfo}); }]),
- (apply [{ return Helper.applyCombineTruncOfExt(*${root}, ${matchinfo}); }])
+ (apply [{ Helper.applyCombineTruncOfExt(*${root}, ${matchinfo}); }])
>;
// Fold trunc (shl x, K) -> shl (trunc x), K => K < VT.getScalarSizeInBits().
@@ -538,7 +538,7 @@ def trunc_shl: GICombineRule <
(defs root:$root, trunc_shl_matchinfo:$matchinfo),
(match (wip_match_opcode G_TRUNC):$root,
[{ return Helper.matchCombineTruncOfShl(*${root}, ${matchinfo}); }]),
- (apply [{ return Helper.applyCombineTruncOfShl(*${root}, ${matchinfo}); }])
+ (apply [{ Helper.applyCombineTruncOfShl(*${root}, ${matchinfo}); }])
>;
// Transform (mul x, -1) -> (sub 0, x)
@@ -546,7 +546,7 @@ def mul_by_neg_one: GICombineRule <
(defs root:$root),
(match (wip_match_opcode G_MUL):$root,
[{ return Helper.matchConstantOp(${root}->getOperand(2), -1); }]),
- (apply [{ return Helper.applyCombineMulByNegativeOne(*${root}); }])
+ (apply [{ Helper.applyCombineMulByNegativeOne(*${root}); }])
>;
// Fold (xor (and x, y), y) -> (and (not x), y)
@@ -556,7 +556,7 @@ def xor_of_and_with_same_reg: GICombineRule <
(defs root:$root, xor_of_and_with_same_reg_matchinfo:$matchinfo),
(match (wip_match_opcode G_XOR):$root,
[{ return Helper.matchXorOfAndWithSameReg(*${root}, ${matchinfo}); }]),
- (apply [{ return Helper.applyXorOfAndWithSameReg(*${root}, ${matchinfo}); }])
+ (apply [{ Helper.applyXorOfAndWithSameReg(*${root}, ${matchinfo}); }])
>;
// Transform (ptr_add 0, x) -> (int_to_ptr x)
@@ -564,27 +564,27 @@ def ptr_add_with_zero: GICombineRule<
(defs root:$root),
(match (wip_match_opcode G_PTR_ADD):$root,
[{ return Helper.matchPtrAddZero(*${root}); }]),
- (apply [{ return Helper.applyPtrAddZero(*${root}); }])>;
+ (apply [{ Helper.applyPtrAddZero(*${root}); }])>;
def regs_small_vec : GIDefMatchData<"SmallVector<Register, 4>">;
def combine_insert_vec_elts_build_vector : GICombineRule<
(defs root:$root, regs_small_vec:$info),
(match (wip_match_opcode G_INSERT_VECTOR_ELT):$root,
[{ return Helper.matchCombineInsertVecElts(*${root}, ${info}); }]),
- (apply [{ return Helper.applyCombineInsertVecElts(*${root}, ${info}); }])>;
+ (apply [{ Helper.applyCombineInsertVecElts(*${root}, ${info}); }])>;
def load_or_combine : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_OR):$root,
[{ return Helper.matchLoadOrCombine(*${root}, ${info}); }]),
- (apply [{ return Helper.applyBuildFn(*${root}, ${info}); }])>;
+ (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def extend_through_phis_matchdata: GIDefMatchData<"MachineInstr*">;
def extend_through_phis : GICombineRule<
(defs root:$root, extend_through_phis_matchdata:$matchinfo),
(match (wip_match_opcode G_PHI):$root,
[{ return Helper.matchExtendThroughPhis(*${root}, ${matchinfo}); }]),
- (apply [{ return Helper.applyExtendThroughPhis(*${root}, ${matchinfo}); }])>;
+ (apply [{ Helper.applyExtendThroughPhis(*${root}, ${matchinfo}); }])>;
// Currently only the one combine above.
def insert_vec_elt_combines : GICombineGroup<
@@ -633,7 +633,7 @@ def bitfield_extract_from_and : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_AND):$root,
[{ return Helper.matchBitfieldExtractFromAnd(*${root}, ${info}); }]),
- (apply [{ return Helper.applyBuildFn(*${root}, ${info}); }])>;
+ (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def funnel_shift_combines : GICombineGroup<[funnel_shift_to_rotate]>;
@@ -641,7 +641,7 @@ def bitfield_extract_from_sext_inreg : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_SEXT_INREG):$root,
[{ return Helper.matchBitfieldExtractFromSExtInReg(*${root}, ${info}); }]),
- (apply [{ return Helper.applyBuildFn(*${root}, ${info}); }])>;
+ (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def form_bitfield_extract : GICombineGroup<[bitfield_extract_from_sext_inreg,
bitfield_extract_from_and]>;
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 9a7150035786..ad1b461db648 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -679,12 +679,11 @@ bool CombinerHelper::matchSextTruncSextLoad(MachineInstr &MI) {
return false;
}
-bool CombinerHelper::applySextTruncSextLoad(MachineInstr &MI) {
+void CombinerHelper::applySextTruncSextLoad(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_SEXT_INREG);
Builder.setInstrAndDebugLoc(MI);
Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchSextInRegOfLoad(
@@ -722,7 +721,7 @@ bool CombinerHelper::matchSextInRegOfLoad(
return true;
}
-bool CombinerHelper::applySextInRegOfLoad(
+void CombinerHelper::applySextInRegOfLoad(
MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_SEXT_INREG);
Register LoadReg;
@@ -745,7 +744,6 @@ bool CombinerHelper::applySextInRegOfLoad(
Builder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, MI.getOperand(0).getReg(),
LoadDef->getOperand(1).getReg(), *NewMMO);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::findPostIndexCandidate(MachineInstr &MI, Register &Addr,
@@ -1691,7 +1689,7 @@ bool CombinerHelper::matchCombineConstantFoldFpUnary(MachineInstr &MI,
return Cst.hasValue();
}
-bool CombinerHelper::applyCombineConstantFoldFpUnary(MachineInstr &MI,
+void CombinerHelper::applyCombineConstantFoldFpUnary(MachineInstr &MI,
Optional<APFloat> &Cst) {
assert(Cst.hasValue() && "Optional is unexpectedly empty!");
Builder.setInstrAndDebugLoc(MI);
@@ -1700,7 +1698,6 @@ bool CombinerHelper::applyCombineConstantFoldFpUnary(MachineInstr &MI,
Register DstReg = MI.getOperand(0).getReg();
Builder.buildFConstant(DstReg, *FPVal);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchPtrAddImmedChain(MachineInstr &MI,
@@ -1743,7 +1740,7 @@ bool CombinerHelper::matchPtrAddImmedChain(MachineInstr &MI,
return true;
}
-bool CombinerHelper::applyPtrAddImmedChain(MachineInstr &MI,
+void CombinerHelper::applyPtrAddImmedChain(MachineInstr &MI,
PtrAddChain &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_PTR_ADD && "Expected G_PTR_ADD");
MachineIRBuilder MIB(MI);
@@ -1753,7 +1750,6 @@ bool CombinerHelper::applyPtrAddImmedChain(MachineInstr &MI,
MI.getOperand(1).setReg(MatchInfo.Base);
MI.getOperand(2).setReg(NewOffset.getReg(0));
Observer.changedInstr(MI);
- return true;
}
bool CombinerHelper::matchShiftImmedChain(MachineInstr &MI,
@@ -1801,7 +1797,7 @@ bool CombinerHelper::matchShiftImmedChain(MachineInstr &MI,
return true;
}
-bool CombinerHelper::applyShiftImmedChain(MachineInstr &MI,
+void CombinerHelper::applyShiftImmedChain(MachineInstr &MI,
RegisterImmPair &MatchInfo) {
unsigned Opcode = MI.getOpcode();
assert((Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_ASHR ||
@@ -1819,7 +1815,7 @@ bool CombinerHelper::applyShiftImmedChain(MachineInstr &MI,
if (Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_LSHR) {
Builder.buildConstant(MI.getOperand(0), 0);
MI.eraseFromParent();
- return true;
+ return;
}
// Arithmetic shift and saturating signed left shift have no effect beyond
// scalar size.
@@ -1832,7 +1828,6 @@ bool CombinerHelper::applyShiftImmedChain(MachineInstr &MI,
MI.getOperand(1).setReg(MatchInfo.Reg);
MI.getOperand(2).setReg(NewImm);
Observer.changedInstr(MI);
- return true;
}
bool CombinerHelper::matchShiftOfShiftedLogic(MachineInstr &MI,
@@ -1916,7 +1911,7 @@ bool CombinerHelper::matchShiftOfShiftedLogic(MachineInstr &MI,
return true;
}
-bool CombinerHelper::applyShiftOfShiftedLogic(MachineInstr &MI,
+void CombinerHelper::applyShiftOfShiftedLogic(MachineInstr &MI,
ShiftOfShiftedLogic &MatchInfo) {
unsigned Opcode = MI.getOpcode();
assert((Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_ASHR ||
@@ -1948,7 +1943,6 @@ bool CombinerHelper::applyShiftOfShiftedLogic(MachineInstr &MI,
MatchInfo.Logic->eraseFromParent();
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineMulToShl(MachineInstr &MI,
@@ -1963,7 +1957,7 @@ bool CombinerHelper::matchCombineMulToShl(MachineInstr &MI,
return (static_cast<int32_t>(ShiftVal) != -1);
}
-bool CombinerHelper::applyCombineMulToShl(MachineInstr &MI,
+void CombinerHelper::applyCombineMulToShl(MachineInstr &MI,
unsigned &ShiftVal) {
assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL");
MachineIRBuilder MIB(MI);
@@ -1973,7 +1967,6 @@ bool CombinerHelper::applyCombineMulToShl(MachineInstr &MI,
MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL));
MI.getOperand(2).setReg(ShiftCst.getReg(0));
Observer.changedInstr(MI);
- return true;
}
// shl ([sza]ext x), y => zext (shl x, y), if shift does not overflow source
@@ -2014,7 +2007,7 @@ bool CombinerHelper::matchCombineShlOfExtend(MachineInstr &MI,
return MinLeadingZeros >= ShiftAmt;
}
-bool CombinerHelper::applyCombineShlOfExtend(MachineInstr &MI,
+void CombinerHelper::applyCombineShlOfExtend(MachineInstr &MI,
const RegisterImmPair &MatchData) {
Register ExtSrcReg = MatchData.Reg;
int64_t ShiftAmtVal = MatchData.Imm;
@@ -2026,7 +2019,6 @@ bool CombinerHelper::applyCombineShlOfExtend(MachineInstr &MI,
Builder.buildShl(ExtSrcTy, ExtSrcReg, ShiftAmt, MI.getFlags());
Builder.buildZExt(MI.getOperand(0), NarrowShift);
MI.eraseFromParent();
- return true;
}
static Register peekThroughBitcast(Register Reg,
@@ -2064,7 +2056,7 @@ bool CombinerHelper::matchCombineUnmergeMergeToPlainValues(
return true;
}
-bool CombinerHelper::applyCombineUnmergeMergeToPlainValues(
+void CombinerHelper::applyCombineUnmergeMergeToPlainValues(
MachineInstr &MI, SmallVectorImpl<Register> &Operands) {
assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
"Expected an unmerge");
@@ -2085,7 +2077,6 @@ bool CombinerHelper::applyCombineUnmergeMergeToPlainValues(
Builder.buildCast(DstReg, SrcReg);
}
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineUnmergeConstant(MachineInstr &MI,
@@ -2113,7 +2104,7 @@ bool CombinerHelper::matchCombineUnmergeConstant(MachineInstr &MI,
return true;
}
-bool CombinerHelper::applyCombineUnmergeConstant(MachineInstr &MI,
+void CombinerHelper::applyCombineUnmergeConstant(MachineInstr &MI,
SmallVectorImpl<APInt> &Csts) {
assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
"Expected an unmerge");
@@ -2127,7 +2118,6 @@ bool CombinerHelper::applyCombineUnmergeConstant(MachineInstr &MI,
}
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) {
@@ -2141,7 +2131,7 @@ bool CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) {
return true;
}
-bool CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) {
+void CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) {
Builder.setInstrAndDebugLoc(MI);
Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg();
// Truncating a vector is going to truncate every single lane,
@@ -2160,7 +2150,6 @@ bool CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) {
} else
Builder.buildTrunc(Dst0Reg, SrcReg);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineUnmergeZExtToZExt(MachineInstr &MI) {
@@ -2189,7 +2178,7 @@ bool CombinerHelper::matchCombineUnmergeZExtToZExt(MachineInstr &MI) {
return ZExtSrcTy.getSizeInBits() <= Dst0Ty.getSizeInBits();
}
-bool CombinerHelper::applyCombineUnmergeZExtToZExt(MachineInstr &MI) {
+void CombinerHelper::applyCombineUnmergeZExtToZExt(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
"Expected an unmerge");
@@ -2221,7 +2210,6 @@ bool CombinerHelper::applyCombineUnmergeZExtToZExt(MachineInstr &MI) {
replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg);
}
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineShiftToUnmerge(MachineInstr &MI,
@@ -2249,7 +2237,7 @@ bool CombinerHelper::matchCombineShiftToUnmerge(MachineInstr &MI,
return ShiftVal >= Size / 2 && ShiftVal < Size;
}
-bool CombinerHelper::applyCombineShiftToUnmerge(MachineInstr &MI,
+void CombinerHelper::applyCombineShiftToUnmerge(MachineInstr &MI,
const unsigned &ShiftVal) {
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
@@ -2320,7 +2308,6 @@ bool CombinerHelper::applyCombineShiftToUnmerge(MachineInstr &MI,
}
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::tryCombineShiftToUnmerge(MachineInstr &MI,
@@ -2343,13 +2330,12 @@ bool CombinerHelper::matchCombineI2PToP2I(MachineInstr &MI, Register &Reg) {
m_GPtrToInt(m_all_of(m_SpecificType(DstTy), m_Reg(Reg))));
}
-bool CombinerHelper::applyCombineI2PToP2I(MachineInstr &MI, Register &Reg) {
+void CombinerHelper::applyCombineI2PToP2I(MachineInstr &MI, Register &Reg) {
assert(MI.getOpcode() == TargetOpcode::G_INTTOPTR && "Expected a G_INTTOPTR");
Register DstReg = MI.getOperand(0).getReg();
Builder.setInstr(MI);
Builder.buildCopy(DstReg, Reg);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineP2IToI2P(MachineInstr &MI, Register &Reg) {
@@ -2358,13 +2344,12 @@ bool CombinerHelper::matchCombineP2IToI2P(MachineInstr &MI, Register &Reg) {
return mi_match(SrcReg, MRI, m_GIntToPtr(m_Reg(Reg)));
}
-bool CombinerHelper::applyCombineP2IToI2P(MachineInstr &MI, Register &Reg) {
+void CombinerHelper::applyCombineP2IToI2P(MachineInstr &MI, Register &Reg) {
assert(MI.getOpcode() == TargetOpcode::G_PTRTOINT && "Expected a G_PTRTOINT");
Register DstReg = MI.getOperand(0).getReg();
Builder.setInstr(MI);
Builder.buildZExtOrTrunc(DstReg, Reg);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineAddP2IToPtrAdd(
@@ -2392,7 +2377,7 @@ bool CombinerHelper::matchCombineAddP2IToPtrAdd(
return false;
}
-bool CombinerHelper::applyCombineAddP2IToPtrAdd(
+void CombinerHelper::applyCombineAddP2IToPtrAdd(
MachineInstr &MI, std::pair<Register, bool> &PtrReg) {
Register Dst = MI.getOperand(0).getReg();
Register LHS = MI.getOperand(1).getReg();
@@ -2409,7 +2394,6 @@ bool CombinerHelper::applyCombineAddP2IToPtrAdd(
auto PtrAdd = Builder.buildPtrAdd(PtrTy, LHS, RHS);
Builder.buildPtrToInt(Dst, PtrAdd);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineConstPtrAddToI2P(MachineInstr &MI,
@@ -2430,7 +2414,7 @@ bool CombinerHelper::matchCombineConstPtrAddToI2P(MachineInstr &MI,
return false;
}
-bool CombinerHelper::applyCombineConstPtrAddToI2P(MachineInstr &MI,
+void CombinerHelper::applyCombineConstPtrAddToI2P(MachineInstr &MI,
int64_t &NewCst) {
assert(MI.getOpcode() == TargetOpcode::G_PTR_ADD && "Expected a G_PTR_ADD");
Register Dst = MI.getOperand(0).getReg();
@@ -2438,7 +2422,6 @@ bool CombinerHelper::applyCombineConstPtrAddToI2P(MachineInstr &MI,
Builder.setInstrAndDebugLoc(MI);
Builder.buildConstant(Dst, NewCst);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) {
@@ -2485,7 +2468,7 @@ bool CombinerHelper::matchCombineExtOfExt(
return false;
}
-bool CombinerHelper::applyCombineExtOfExt(
+void CombinerHelper::applyCombineExtOfExt(
MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) {
assert((MI.getOpcode() == TargetOpcode::G_ANYEXT ||
MI.getOpcode() == TargetOpcode::G_SEXT ||
@@ -2500,7 +2483,7 @@ bool CombinerHelper::applyCombineExtOfExt(
Observer.changingInstr(MI);
MI.getOperand(1).setReg(Reg);
Observer.changedInstr(MI);
- return true;
+ return;
}
// Combine:
@@ -2513,13 +2496,10 @@ bool CombinerHelper::applyCombineExtOfExt(
Builder.setInstrAndDebugLoc(MI);
Builder.buildInstr(SrcExtOp, {DstReg}, {Reg});
MI.eraseFromParent();
- return true;
}
-
- return false;
}
-bool CombinerHelper::applyCombineMulByNegativeOne(MachineInstr &MI) {
+void CombinerHelper::applyCombineMulByNegativeOne(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL");
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
@@ -2529,7 +2509,6 @@ bool CombinerHelper::applyCombineMulByNegativeOne(MachineInstr &MI) {
Builder.buildSub(DstReg, Builder.buildConstant(DstTy, 0), SrcReg,
MI.getFlags());
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg) {
@@ -2559,7 +2538,7 @@ bool CombinerHelper::matchCombineTruncOfExt(
return false;
}
-bool CombinerHelper::applyCombineTruncOfExt(
+void CombinerHelper::applyCombineTruncOfExt(
MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC");
Register SrcReg = MatchInfo.first;
@@ -2570,7 +2549,7 @@ bool CombinerHelper::applyCombineTruncOfExt(
if (SrcTy == DstTy) {
MI.eraseFromParent();
replaceRegWith(MRI, DstReg, SrcReg);
- return true;
+ return;
}
Builder.setInstrAndDebugLoc(MI);
if (SrcTy.getSizeInBits() < DstTy.getSizeInBits())
@@ -2578,7 +2557,6 @@ bool CombinerHelper::applyCombineTruncOfExt(
else
Builder.buildTrunc(DstReg, SrcReg);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchCombineTruncOfShl(
@@ -2605,7 +2583,7 @@ bool CombinerHelper::matchCombineTruncOfShl(
return false;
}
-bool CombinerHelper::applyCombineTruncOfShl(
+void CombinerHelper::applyCombineTruncOfShl(
MachineInstr &MI, std::pair<Register, Register> &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC");
Register DstReg = MI.getOperand(0).getReg();
@@ -2619,7 +2597,6 @@ bool CombinerHelper::applyCombineTruncOfShl(
auto TruncShiftSrc = Builder.buildTrunc(DstTy, ShiftSrc);
Builder.buildShl(DstReg, TruncShiftSrc, ShiftAmt, SrcMI->getFlags());
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) {
@@ -2887,7 +2864,7 @@ bool CombinerHelper::matchCombineInsertVecElts(
return TmpInst->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
}
-bool CombinerHelper::applyCombineInsertVecElts(
+void CombinerHelper::applyCombineInsertVecElts(
MachineInstr &MI, SmallVectorImpl<Register> &MatchInfo) {
Builder.setInstr(MI);
Register UndefReg;
@@ -2904,17 +2881,15 @@ bool CombinerHelper::applyCombineInsertVecElts(
}
Builder.buildBuildVector(MI.getOperand(0).getReg(), MatchInfo);
MI.eraseFromParent();
- return true;
}
-bool CombinerHelper::applySimplifyAddToSub(
+void CombinerHelper::applySimplifyAddToSub(
MachineInstr &MI, std::tuple<Register, Register> &MatchInfo) {
Builder.setInstr(MI);
Register SubLHS, SubRHS;
std::tie(SubLHS, SubRHS) = MatchInfo;
Builder.buildSub(MI.getOperand(0).getReg(), SubLHS, SubRHS);
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(
@@ -3008,7 +2983,7 @@ bool CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(
return true;
}
-bool CombinerHelper::applyBuildInstructionSteps(
+void CombinerHelper::applyBuildInstructionSteps(
MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) {
assert(MatchInfo.InstrsToBuild.size() &&
"Expected at least one instr to build?");
@@ -3021,7 +2996,6 @@ bool CombinerHelper::applyBuildInstructionSteps(
OperandFn(Instr);
}
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchAshrShlToSextInreg(
@@ -3041,7 +3015,8 @@ bool CombinerHelper::matchAshrShlToSextInreg(
MatchInfo = std::make_tuple(Src, ShlCst);
return true;
}
-bool CombinerHelper::applyAshShlToSextInreg(
+
+void CombinerHelper::applyAshShlToSextInreg(
MachineInstr &MI, std::tuple<Register, int64_t> &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_ASHR);
Register Src;
@@ -3051,7 +3026,6 @@ bool CombinerHelper::applyAshShlToSextInreg(
Builder.setInstrAndDebugLoc(MI);
Builder.buildSExtInReg(MI.getOperand(0).getReg(), Src, Size - ShiftAmt);
MI.eraseFromParent();
- return true;
}
/// and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
@@ -3274,7 +3248,7 @@ bool CombinerHelper::matchNotCmp(MachineInstr &MI,
return true;
}
-bool CombinerHelper::applyNotCmp(MachineInstr &MI,
+void CombinerHelper::applyNotCmp(MachineInstr &MI,
SmallVectorImpl<Register> &RegsToNegate) {
for (Register Reg : RegsToNegate) {
MachineInstr *Def = MRI.getVRegDef(Reg);
@@ -3304,7 +3278,6 @@ bool CombinerHelper::applyNotCmp(MachineInstr &MI,
replaceRegWith(MRI, MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
MI.eraseFromParent();
- return true;
}
bool CombinerHelper::matchXorOfAndWithSameReg(
@@ -3338,7 +3311,7 @@ bool CombinerHelper::matchXorOfAndWithSameReg(
return Y == SharedReg;
}
-bool CombinerHelper::applyXorOfAndWithSameReg(
+void CombinerHelper::applyXorOfAndWithSameReg(
MachineInstr &MI, std::pair<Register, Register> &MatchInfo) {
// Fold (xor (and x, y), y) -> (and (not x), y)
Builder.setInstrAndDebugLoc(MI);
@@ -3350,7 +3323,6 @@ bool CombinerHelper::applyXorOfAndWithSameReg(
MI.getOperand(1).setReg(Not->getOperand(0).getReg());
MI.getOperand(2).setReg(Y);
Observer.changedInstr(MI);
- return true;
}
bool CombinerHelper::matchPtrAddZero(MachineInstr &MI) {
@@ -3371,16 +3343,15 @@ bool CombinerHelper::matchPtrAddZero(MachineInstr &MI) {
return isBuildVectorAllZeros(*VecMI, MRI);
}
-bool CombinerHelper::applyPtrAddZero(MachineInstr &MI) {
+void CombinerHelper::applyPtrAddZero(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_PTR_ADD);
Builder.setInstrAndDebugLoc(MI);
Builder.buildIntToPtr(MI.getOperand(0), MI.getOperand(2));
MI.eraseFromParent();
- return true;
}
/// The second source operand is known to be a power of 2.
-bool CombinerHelper::applySimplifyURemByPow2(MachineInstr &MI) {
+void CombinerHelper::applySimplifyURemByPow2(MachineInstr &MI) {
Register DstReg = MI.getOperand(0).getReg();
Register Src0 = MI.getOperand(1).getReg();
Register Pow2Src1 = MI.getOperand(2).getReg();
@@ -3392,7 +3363,6 @@ bool CombinerHelper::applySimplifyURemByPow2(MachineInstr &MI) {
auto Add = Builder.buildAdd(Ty, Pow2Src1, NegOne);
Builder.buildAnd(DstReg, Src0, Add);
MI.eraseFromParent();
- return true;
}
Optional<SmallVector<Register, 8>>
@@ -3797,7 +3767,7 @@ bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI,
return true;
}
-bool CombinerHelper::applyExtendThroughPhis(MachineInstr &MI,
+void CombinerHelper::applyExtendThroughPhis(MachineInstr &MI,
MachineInstr *&ExtMI) {
assert(MI.getOpcode() == TargetOpcode::G_PHI);
Register DstReg = ExtMI->getOperand(0).getReg();
@@ -3841,7 +3811,6 @@ bool CombinerHelper::applyExtendThroughPhis(MachineInstr &MI,
}
Builder.insertInstr(NewPhi);
ExtMI->eraseFromParent();
- return true;
}
bool CombinerHelper::matchExtractVecEltBuildVec(MachineInstr &MI,
@@ -3954,19 +3923,17 @@ void CombinerHelper::applyExtractAllEltsFromBuildVector(
MI.eraseFromParent();
}
-bool CombinerHelper::applyBuildFn(
+void CombinerHelper::applyBuildFn(
MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
Builder.setInstrAndDebugLoc(MI);
MatchInfo(Builder);
MI.eraseFromParent();
- return true;
}
-bool CombinerHelper::applyBuildFnNoErase(
+void CombinerHelper::applyBuildFnNoErase(
MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
Builder.setInstrAndDebugLoc(MI);
MatchInfo(Builder);
- return true;
}
/// Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
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