[PATCH] D105347: [AMDGPU][GlobalISel] Legalization and selection of G_ROTL and G_ROTR

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/VOP3Instructions.td:346
+  (rotr i32:$src0, i32:$src1),
+  (V_ALIGNBIT_B32_e64 VGPR_32:$src0, VGPR_32:$src0, VGPR_32:$src1)
+>;
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Isn't there a lowering to turn this into fshr? Why do we need to directly select this?


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/rotate_pre_instselect.mir:6
+--- |
+  ; ModuleID = '../llvm/test/CodeGen/AMDGPU/GlobalISel/rotl_rotr.ll'
+  source_filename = "../llvm/test/CodeGen/AMDGPU/GlobalISel/rotl_rotr.ll"
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Don't need the IR section, registers section or most of the MIR extras here


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/rotate_pre_regbankselect.mir:713
+    $sgpr2 = COPY %18(s32)
+    %19:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %31(s32)
+    $sgpr3 = COPY %19(s32)
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You can simplify out stuff like this, for the purpose of this test it doesn't need the readlanes


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105347/new/

https://reviews.llvm.org/D105347