[PATCH] D105344: [DAGCombiner] Fold SETCC(FREEZE(x), y) to SETCC(x, y) if used by BRCOND

[Juneyoung Lee via Phabricator via llvm-commits]

aqjune created this revision.
aqjune added reviewers: efriedma, nikic, RKSimon, xbolva00, craig.topper.
Herald added subscribers: ecnelises, pengfei, hiraditya.
aqjune requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch adds a peephole optimization `BRCOND(SETCC(FREEZE(x),y))` => `BRCOND(SETCC(x,y))`.

This leads to a nice improvement in the generated assembly when it is a loaded value.

Its validity is based on D92015 <https://reviews.llvm.org/D92015>, which states that branching on UNDEF is okay in SelDag & adds `BRCOND(FREEZE(cond))` => `BRCOND(cond)` as well.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105344

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/setcc-freeze.ll


Index: llvm/test/CodeGen/X86/setcc-freeze.ll
===================================================================
--- llvm/test/CodeGen/X86/setcc-freeze.ll
+++ llvm/test/CodeGen/X86/setcc-freeze.ll
@@ -4,9 +4,7 @@
 define i32 @f(i16* %p) {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movzwl (%rdi), %eax
-; CHECK-NEXT:    andl $2048, %eax # imm = 0x800
-; CHECK-NEXT:    testw %ax, %ax
+; CHECK-NEXT:    testb $8, 1(%rdi)
 ; CHECK-NEXT:    je .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %B
 ; CHECK-NEXT:    movl $20, %eax
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10152,9 +10152,30 @@
   bool PreferSetCC =
       N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND;
 
+  ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
+  EVT VT = N->getValueType(0);
+
+  // BRCOND(SETCC(FREEZE(a), b)) is equivalent to
+  // BRCOND(SETCC(a, b)) (both are nondeterministic jumps).
+  if (PreferSetCC) {
+    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
+    bool Updated = false;
+
+    if (N0->getOpcode() == ISD::FREEZE && N0.hasOneUse()) {
+      N0 = N0->getOperand(0);
+      Updated = true;
+    }
+    if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) {
+      N1 = N1->getOperand(0);
+      Updated = true;
+    }
+
+    if (Updated)
+      return DAG.getSetCC(SDLoc(N), VT, N0, N1, Cond);
+  }
+
   SDValue Combined = SimplifySetCC(
-      N->getValueType(0), N->getOperand(0), N->getOperand(1),
-      cast<CondCodeSDNode>(N->getOperand(2))->get(), SDLoc(N), !PreferSetCC);
+      VT, N->getOperand(0), N->getOperand(1), Cond, SDLoc(N), !PreferSetCC);
 
   if (!Combined)
     return SDValue();


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