[llvm] 32a7319 - Mips/GlobalISel: Use accurate memory LLTs

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-07-01T20:08:14-04:00
New Revision: 32a73198fc3a84364996c2d8bf2e6470d2bb98d9

URL: https://github.com/llvm/llvm-project/commit/32a73198fc3a84364996c2d8bf2e6470d2bb98d9
DIFF: https://github.com/llvm/llvm-project/commit/32a73198fc3a84364996c2d8bf2e6470d2bb98d9.diff

LOG: Mips/GlobalISel: Use accurate memory LLTs

Added: 
    

Modified: 
    llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
    llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index a3970781ccece..588b7e85c94c7 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -516,13 +516,14 @@ bool MipsLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
   }
   case Intrinsic::vacopy: {
     MachinePointerInfo MPO;
+    LLT PtrTy = LLT::pointer(0, 32);
     auto Tmp =
-        MIRBuilder.buildLoad(LLT::pointer(0, 32), MI.getOperand(2),
+        MIRBuilder.buildLoad(PtrTy, MI.getOperand(2),
                              *MI.getMF()->getMachineMemOperand(
-                                 MPO, MachineMemOperand::MOLoad, 4, Align(4)));
+                                 MPO, MachineMemOperand::MOLoad, PtrTy, Align(4)));
     MIRBuilder.buildStore(Tmp, MI.getOperand(1),
                           *MI.getMF()->getMachineMemOperand(
-                              MPO, MachineMemOperand::MOStore, 4, Align(4)));
+                              MPO, MachineMemOperand::MOStore, PtrTy, Align(4)));
     MI.eraseFromParent();
     return true;
   }

diff  --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
index 3924d914fc62f..dfda755bff268 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
@@ -72,8 +72,8 @@ body:             |
     ; MIPS32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.s
     ; MIPS32: G_STORE [[COPY]](p0), [[FRAME_INDEX3]](p0) :: (store (p0) into %ir.fmt.addr)
     ; MIPS32: G_VASTART [[FRAME_INDEX4]](p0) :: (store (p0) into %ir.ap1, align 1)
-    ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX4]](p0) :: (load (s32))
-    ; MIPS32: G_STORE [[LOAD]](p0), [[FRAME_INDEX5]](p0) :: (store (s32))
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX4]](p0) :: (load (p0))
+    ; MIPS32: G_STORE [[LOAD]](p0), [[FRAME_INDEX5]](p0) :: (store (p0))
     ; MIPS32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (load (p0) from %ir.aq)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
     ; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD1]], [[C]](s32)