[llvm] 71d5b0a - [AArch64][GlobalISel]Legalise some vector types for min/max

[Irina Dobrescu via llvm-commits]

Author: Irina Dobrescu
Date: 2021-07-01T16:29:38+01:00
New Revision: 71d5b0a7572010e07430dd0c3c79bb6c4ebfdfac

URL: https://github.com/llvm/llvm-project/commit/71d5b0a7572010e07430dd0c3c79bb6c4ebfdfac
DIFF: https://github.com/llvm/llvm-project/commit/71d5b0a7572010e07430dd0c3c79bb6c4ebfdfac.diff

LOG: [AArch64][GlobalISel]Legalise some vector types for min/max

Differential Revision: https://reviews.llvm.org/D105200

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index e2532b23e81a2..69be7fb94778b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -168,6 +168,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
 
   getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
+      .legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
       .lowerIf([=](const LegalityQuery &Q) { return Q.Types[0].isScalar(); });
 
   getActionDefinitionsBuilder(

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
new file mode 100644
index 0000000000000..5510b6d243929
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
@@ -0,0 +1,130 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            v8s8_smin
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: v8s8_smin
+    ; CHECK: liveins: $x0
+    ; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
+    ; CHECK: $x0 = COPY %smin(<8 x s8>)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %vec:_(<8 x s8>) = G_IMPLICIT_DEF
+    %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
+    %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
+    $x0 = COPY %smin
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            v16s8_smin
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: v16s8_smin
+    ; CHECK: liveins: $q0
+    ; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
+    ; CHECK: $q0 = COPY %smin(<16 x s8>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %vec:_(<16 x s8>) = G_IMPLICIT_DEF
+    %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
+    %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
+    $q0 = COPY %smin
+    RET_ReallyLR implicit $q0
+
+...
+---
+name:            v4s16_smin
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: v4s16_smin
+    ; CHECK: liveins: $x0
+    ; CHECK: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: %smin:_(<4 x s16>) = G_SMIN %vec, %vec1
+    ; CHECK: $x0 = COPY %smin(<4 x s16>)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %vec:_(<4 x s16>) = G_IMPLICIT_DEF
+    %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
+    %smin:_(<4 x s16>) = G_SMIN %vec, %vec1
+    $x0 = COPY %smin
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            v8s16_smin
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: v8s16_smin
+    ; CHECK: liveins: $q0
+    ; CHECK: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: %smin:_(<8 x s16>) = G_SMIN %vec, %vec1
+    ; CHECK: $q0 = COPY %smin(<8 x s16>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %vec:_(<8 x s16>) = G_IMPLICIT_DEF
+    %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
+    %smin:_(<8 x s16>) = G_SMIN %vec, %vec1
+    $q0 = COPY %smin
+    RET_ReallyLR implicit $q0
+
+...
+---
+name:            v2s32_smin
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: v2s32_smin
+    ; CHECK: liveins: $x0
+    ; CHECK: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: %smin:_(<2 x s32>) = G_SMIN %vec, %vec1
+    ; CHECK: $x0 = COPY %smin(<2 x s32>)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %vec:_(<2 x s32>) = G_IMPLICIT_DEF
+    %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
+    %smin:_(<2 x s32>) = G_SMIN %vec, %vec1
+    $x0 = COPY %smin
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            v4s32_smin
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: v4s32_smin
+    ; CHECK: liveins: $q0
+    ; CHECK: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: %smin:_(<4 x s32>) = G_SMIN %vec, %vec1
+    ; CHECK: $q0 = COPY %smin(<4 x s32>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %vec:_(<4 x s32>) = G_IMPLICIT_DEF
+    %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
+    %smin:_(<4 x s32>) = G_SMIN %vec, %vec1
+    $q0 = COPY %smin
+    RET_ReallyLR implicit $q0
+
+...
+