[PATCH] D105282: [ASan][AMDGPU] Make shadow offset match X86 on Linux

[Reshabh Sharma via Phabricator via llvm-commits]

rksharma created this revision.
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Herald added subscribers: kerbowa, pengfei, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
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We need to match the shadow memory offset with that of the host (X86) on Linux. Setting IsX86 did not work because we can not tell if we are running on Linux from our target triple. This patch explicitly sets the shadow offset with the desired value.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105282

Files:
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
  llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
  llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll


Index: llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
===================================================================
--- llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
+++ llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
@@ -10,7 +10,7 @@
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   or
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
@@ -40,7 +40,7 @@
 ;
 ; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64
 ; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   {{add|or}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
Index: llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
===================================================================
--- llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
+++ llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
@@ -16,7 +16,7 @@
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
@@ -53,7 +53,7 @@
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
Index: llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
===================================================================
--- llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
+++ llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
@@ -12,7 +12,7 @@
 ;
 ; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(4)* %a to i64
 ; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
Index: llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
===================================================================
--- llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -465,10 +465,6 @@
   bool IsEmscripten = TargetTriple.isOSEmscripten();
   bool IsAMDGPU = TargetTriple.isAMDGPU();
 
-  // Asan support for AMDGPU assumes X86 as the host right now.
-  if (IsAMDGPU)
-    IsX86_64 = true;
-
   ShadowMapping Mapping;
 
   Mapping.Scale = kDefaultShadowScale;
@@ -532,6 +528,9 @@
       Mapping.Offset = kAArch64_ShadowOffset64;
     else if (IsRISCV64)
       Mapping.Offset = kRISCV64_ShadowOffset64;
+    else if (IsAMDGPU)
+      Mapping.Offset = (kSmallX86_64ShadowOffsetBase &
+                        (kSmallX86_64ShadowOffsetAlignMask << Mapping.Scale));
     else
       Mapping.Offset = kDefaultShadowOffset64;
   }


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