[PATCH] D103170: [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory
Peter Waller via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 1 04:26:14 PDT 2021
peterwaller-arm updated this revision to Diff 355832.
peterwaller-arm edited the summary of this revision.
peterwaller-arm added a comment.
Apologies for delayed response. Should be much faster on further updates.
- Address most review comments.
- Fix the issue of stack objects.
- Force offset to zero in SelectAddrModeIndexedUImm.
- Add a mir test for frame lowering, which crashes on main and passes here.
- Drop addition of azextload and use more specific patterns instead. I couldn't find a sense in which they were necessary.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D103170/new/
https://reviews.llvm.org/D103170
Files:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
llvm/test/CodeGen/AArch64/sve-ld1r.ll
llvm/test/CodeGen/AArch64/sve-ld1r.mir
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