[PATCH] D105253: GlobalISel: Handle lowering non-power-of-2 extloads

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir:15738
+    ; CI-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
+    ; CI-HSA: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+    ; CI-HSA: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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Why does this extend to s64 for the shifting and ORing?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105253/new/

https://reviews.llvm.org/D105253