[llvm] f0693bc - autogen two tests for ease of update
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 30 11:47:42 PDT 2021
Author: Philip Reames
Date: 2021-06-30T11:47:36-07:00
New Revision: f0693bc0ae47e4f7237e4e8d17ee96481c370e0a
URL: https://github.com/llvm/llvm-project/commit/f0693bc0ae47e4f7237e4e8d17ee96481c370e0a
DIFF: https://github.com/llvm/llvm-project/commit/f0693bc0ae47e4f7237e4e8d17ee96481c370e0a.diff
LOG: autogen two tests for ease of update
Added:
Modified:
llvm/test/Transforms/LoopReroll/nonconst_lb.ll
llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopReroll/nonconst_lb.ll b/llvm/test/Transforms/LoopReroll/nonconst_lb.ll
index aa5c456362676..200a37b8eed52 100644
--- a/llvm/test/Transforms/LoopReroll/nonconst_lb.ll
+++ b/llvm/test/Transforms/LoopReroll/nonconst_lb.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -loop-reroll -S | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-none-linux"
@@ -11,6 +12,33 @@ target triple = "thumbv7-none-linux"
; }
;}
define void @foo(i32* nocapture %A, i32* nocapture readonly %B, i32 %m, i32 %n) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP34:%.*]] = icmp slt i32 [[M:%.*]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[CMP34]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
+; CHECK: for.body.preheader:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[M]]
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP2]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 3
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[M]], [[INDVAR]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = shl nsw i32 [[TMP6]], 2
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[TMP5]]
+; CHECK-NEXT: store i32 [[MUL]], i32* [[ARRAYIDX2]], align 4
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVAR]], [[TMP4]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY]]
+; CHECK: for.end.loopexit:
+; CHECK-NEXT: br label [[FOR_END]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%cmp34 = icmp slt i32 %m, %n
br i1 %cmp34, label %for.body, label %for.end
@@ -47,26 +75,6 @@ for.body: ; preds = %entry, %for.body
for.end: ; preds = %for.body, %entry
ret void
}
-; CHECK-LABEL: @foo
-; CHECK: for.body.preheader:
-; CHECK: %0 = add i32 %n, -1
-; CHECK: %1 = sub i32 %0, %m
-; CHECK: %2 = lshr i32 %1, 2
-; CHECK: %3 = shl nuw i32 %2, 2
-; CHECK: %4 = add nuw nsw i32 %3, 3
-; CHECK: br label %for.body
-
-; CHECK: for.body:
-; CHECK: %indvar = phi i32 [ 0, %for.body.preheader ], [ %indvar.next, %for.body ]
-; CHECK: %5 = add i32 %m, %indvar
-; CHECK: %arrayidx = getelementptr inbounds i32, i32* %B, i32 %5
-; CHECK: %6 = load i32, i32* %arrayidx, align 4
-; CHECK: %mul = shl nsw i32 %6, 2
-; CHECK: %arrayidx2 = getelementptr inbounds i32, i32* %A, i32 %5
-; CHECK: store i32 %mul, i32* %arrayidx2, align 4
-; CHECK: %indvar.next = add i32 %indvar, 1
-; CHECK: %exitcond = icmp eq i32 %indvar, %4
-; CHECK: br i1 %exitcond, label %for.end.loopexit, label %for.body
;void daxpy_ur(int n,float da,float *dx,float *dy)
; {
@@ -80,6 +88,36 @@ for.end: ; preds = %for.body, %entry
; }
; }
define void @daxpy_ur(i32 %n, float %da, float* nocapture readonly %dx, float* nocapture %dy) {
+; CHECK-LABEL: @daxpy_ur(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[N:%.*]], 4
+; CHECK-NEXT: [[CMP55:%.*]] = icmp slt i32 [[REM]], [[N]]
+; CHECK-NEXT: br i1 [[CMP55]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
+; CHECK: for.body.preheader:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[REM]]
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP2]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 3
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[REM]], [[INDVAR]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[DY:%.*]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[DX:%.*]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX1]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP7]], [[DA:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP6]], [[MUL]]
+; CHECK-NEXT: store float [[ADD]], float* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVAR]], [[TMP4]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY]]
+; CHECK: for.end.loopexit:
+; CHECK-NEXT: br label [[FOR_END]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%rem = srem i32 %n, 4
%cmp55 = icmp slt i32 %rem, %n
@@ -126,25 +164,3 @@ for.end: ; preds = %for.body, %entry
ret void
}
-; CHECK-LABEL: @daxpy_ur
-; CHECK: for.body.preheader:
-; CHECK: %0 = add i32 %n, -1
-; CHECK: %1 = sub i32 %0, %rem
-; CHECK: %2 = lshr i32 %1, 2
-; CHECK: %3 = shl nuw i32 %2, 2
-; CHECK: %4 = add nuw nsw i32 %3, 3
-; CHECK: br label %for.body
-
-; CHECK: for.body:
-; CHECK: %indvar = phi i32 [ 0, %for.body.preheader ], [ %indvar.next, %for.body ]
-; CHECK: %5 = add i32 %rem, %indvar
-; CHECK: %arrayidx = getelementptr inbounds float, float* %dy, i32 %5
-; CHECK: %6 = load float, float* %arrayidx, align 4
-; CHECK: %arrayidx1 = getelementptr inbounds float, float* %dx, i32 %5
-; CHECK: %7 = load float, float* %arrayidx1, align 4
-; CHECK: %mul = fmul float %7, %da
-; CHECK: %add = fadd float %6, %mul
-; CHECK: store float %add, float* %arrayidx, align 4
-; CHECK: %indvar.next = add i32 %indvar, 1
-; CHECK: %exitcond = icmp eq i32 %indvar, %4
-; CHECK: br i1 %exitcond, label %for.end.loopexit, label %for.body
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
index 5b8e5ef7fd1f4..9110650a93342 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=false -unroll-runtime-multi-exit=true -unroll-count=4 -verify-dom-info -S | FileCheck %s
; REQUIRES: asserts
@@ -8,16 +9,55 @@
; mergedexit block has edges from loop exit blocks.
define i64 @test1() {
-; CHECK-LABEL: test1(
-; CHECK-LABEL: headerexit:
-; CHECK-NEXT: %addphi = phi i64 [ %add.iv, %header ], [ %add.iv.1, %header.1 ], [ %add.iv.2, %header.2 ], [ %add.iv.3, %header.3 ]
-; CHECK-NEXT: br label %mergedexit
-; CHECK-LABEL: latchexit:
-; CHECK-NEXT: %shftphi = phi i64 [ %shft, %latch ], [ %shft.1, %latch.1 ], [ %shft.2, %latch.2 ], [ %shft.3, %latch.3 ]
-; CHECK-NEXT: br label %mergedexit
-; CHECK-LABEL: mergedexit:
-; CHECK-NEXT: %retval = phi i64 [ %addphi, %headerexit ], [ %shftphi, %latchexit ]
-; CHECK-NEXT: ret i64 %retval
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[PREHEADER:%.*]]
+; CHECK: preheader:
+; CHECK-NEXT: [[TRIP:%.*]] = zext i32 undef to i64
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ]
+; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
+; CHECK: latch:
+; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
+; CHECK: headerexit:
+; CHECK-NEXT: [[ADDPHI:%.*]] = phi i64 [ [[ADD_IV]], [[HEADER]] ], [ [[ADD_IV_1:%.*]], [[HEADER_1]] ], [ [[ADD_IV_2:%.*]], [[HEADER_2:%.*]] ], [ [[ADD_IV_3]], [[HEADER_3:%.*]] ]
+; CHECK-NEXT: br label [[MERGEDEXIT:%.*]]
+; CHECK: latchexit:
+; CHECK-NEXT: [[SHFTPHI:%.*]] = phi i64 [ [[SHFT]], [[LATCH]] ], [ [[SHFT_1:%.*]], [[LATCH_1:%.*]] ], [ [[SHFT_2:%.*]], [[LATCH_2:%.*]] ], [ [[SHFT_3:%.*]], [[LATCH_3]] ]
+; CHECK-NEXT: br label [[MERGEDEXIT]]
+; CHECK: mergedexit:
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[ADDPHI]], [[HEADEREXIT]] ], [ [[SHFTPHI]], [[LATCHEXIT]] ]
+; CHECK-NEXT: ret i64 [[RETVAL]]
+; CHECK: header.1:
+; CHECK-NEXT: [[ADD_IV_1]] = add nuw nsw i64 [[ADD_IV]], 2
+; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1]], label [[HEADEREXIT]]
+; CHECK: latch.1:
+; CHECK-NEXT: [[SHFT_1]] = ashr i64 [[ADD_IV_1]], 1
+; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2]], label [[LATCHEXIT]]
+; CHECK: header.2:
+; CHECK-NEXT: [[ADD_IV_2]] = add nuw nsw i64 [[ADD_IV_1]], 2
+; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2]], label [[HEADEREXIT]]
+; CHECK: latch.2:
+; CHECK-NEXT: [[SHFT_2]] = ashr i64 [[ADD_IV_2]], 1
+; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3]], label [[LATCHEXIT]]
+; CHECK: header.3:
+; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2
+; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
+; CHECK: latch.3:
+; CHECK-NEXT: [[SHFT_3]] = ashr i64 [[ADD_IV_3]], 1
+; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP0:![0-9]+]]
+;
entry:
br label %preheader
@@ -41,7 +81,7 @@ headerexit: ; preds = %header
br label %mergedexit
latchexit: ; preds = %latch
- %shftphi = phi i64 [ %shft, %latch ]
+ %shftphi = phi i64 [ %shft, %latch ]
br label %mergedexit
mergedexit: ; preds = %latchexit, %headerexit
@@ -51,12 +91,52 @@ mergedexit: ; preds = %latchexit, %
; mergedexit has edges from loop exit blocks and a block outside the loop.
define void @test2(i1 %cond, i32 %n) {
-; CHECK-LABEL: header.1:
-; CHECK-NEXT: %add.iv.1 = add nuw nsw i64 %add.iv, 2
-; CHECK: br i1 %cmp1.1, label %latch.1, label %headerexit
-; CHECK-LABEL: latch.3:
-; CHECK: %cmp2.3 = icmp ult i64 %shft.3, %trip
-; CHECK-NEXT: br i1 %cmp2.3, label %header, label %latchexit, !llvm.loop
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[PREHEADER:%.*]], label [[MERGEDEXIT:%.*]]
+; CHECK: preheader:
+; CHECK-NEXT: [[TRIP:%.*]] = zext i32 [[N:%.*]] to i64
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ]
+; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
+; CHECK: latch:
+; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
+; CHECK: headerexit:
+; CHECK-NEXT: br label [[MERGEDEXIT]]
+; CHECK: latchexit:
+; CHECK-NEXT: br label [[MERGEDEXIT]]
+; CHECK: mergedexit:
+; CHECK-NEXT: ret void
+; CHECK: header.1:
+; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2
+; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]]
+; CHECK: latch.1:
+; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1
+; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]]
+; CHECK: header.2:
+; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2
+; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]]
+; CHECK: latch.2:
+; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1
+; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]]
+; CHECK: header.3:
+; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2
+; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
+; CHECK: latch.3:
+; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1
+; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP2:![0-9]+]]
+;
entry:
br i1 %cond, label %preheader, label %mergedexit
@@ -88,14 +168,53 @@ mergedexit: ; preds = %latchexit, %
; exitsucc is from loop exit block only.
define i64 @test3(i32 %n) {
-; CHECK-LABEL: test3(
-; CHECK-LABEL: headerexit:
-; CHECK-NEXT: br label %exitsucc
-; CHECK-LABEL: latchexit:
-; CHECK-NEXT: %shftphi = phi i64 [ %shft, %latch ], [ %shft.1, %latch.1 ], [ %shft.2, %latch.2 ], [ %shft.3, %latch.3 ]
-; CHECK-NEXT: ret i64 %shftphi
-; CHECK-LABEL: exitsucc:
-; CHECK-NEXT: ret i64 96
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[PREHEADER:%.*]]
+; CHECK: preheader:
+; CHECK-NEXT: [[TRIP:%.*]] = zext i32 [[N:%.*]] to i64
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ]
+; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
+; CHECK: latch:
+; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
+; CHECK: headerexit:
+; CHECK-NEXT: br label [[EXITSUCC:%.*]]
+; CHECK: latchexit:
+; CHECK-NEXT: [[SHFTPHI:%.*]] = phi i64 [ [[SHFT]], [[LATCH]] ], [ [[SHFT_1:%.*]], [[LATCH_1:%.*]] ], [ [[SHFT_2:%.*]], [[LATCH_2:%.*]] ], [ [[SHFT_3:%.*]], [[LATCH_3]] ]
+; CHECK-NEXT: ret i64 [[SHFTPHI]]
+; CHECK: exitsucc:
+; CHECK-NEXT: ret i64 96
+; CHECK: header.1:
+; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2
+; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1]], label [[HEADEREXIT]]
+; CHECK: latch.1:
+; CHECK-NEXT: [[SHFT_1]] = ashr i64 [[ADD_IV_1]], 1
+; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]]
+; CHECK: header.2:
+; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2
+; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2]], label [[HEADEREXIT]]
+; CHECK: latch.2:
+; CHECK-NEXT: [[SHFT_2]] = ashr i64 [[ADD_IV_2]], 1
+; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]]
+; CHECK: header.3:
+; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2
+; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
+; CHECK: latch.3:
+; CHECK-NEXT: [[SHFT_3]] = ashr i64 [[ADD_IV_3]], 1
+; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
+; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP3:![0-9]+]]
+;
entry:
br label %preheader
@@ -127,22 +246,95 @@ exitsucc: ; preds = %headerexit
; exit block (%default) has an exiting block and another exit block as predecessors.
define void @test4(i16 %c3) {
-; CHECK-LABEL: test4
-
-; CHECK-LABEL: exiting.prol:
-; CHECK-NEXT: switch i16 %c3, label %default.loopexit.loopexit1 [
-
-; CHECK-LABEL: exiting:
-; CHECK-NEXT: switch i16 %c3, label %default.loopexit.loopexit [
-
-; CHECK-LABEL: default.loopexit.loopexit:
-; CHECK-NEXT: br label %default.loopexit
-
-; CHECK-LABEL: default.loopexit.loopexit1:
-; CHECK-NEXT: br label %default.loopexit
-
-; CHECK-LABEL: default.loopexit:
-; CHECK-NEXT: br label %default
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: preheader:
+; CHECK-NEXT: [[C1:%.*]] = zext i32 undef to i64
+; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[C1]], i64 1)
+; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[UMAX]], -1
+; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[UMAX]], 3
+; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
+; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[HEADER_PROL_PREHEADER:%.*]], label [[HEADER_PROL_LOOPEXIT:%.*]]
+; CHECK: header.prol.preheader:
+; CHECK-NEXT: br label [[HEADER_PROL:%.*]]
+; CHECK: header.prol:
+; CHECK-NEXT: [[INDVARS_IV_PROL:%.*]] = phi i64 [ 0, [[HEADER_PROL_PREHEADER]] ], [ [[INDVARS_IV_NEXT_PROL:%.*]], [[LATCH_PROL:%.*]] ]
+; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ [[XTRAITER]], [[HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[LATCH_PROL]] ]
+; CHECK-NEXT: br label [[EXITING_PROL:%.*]]
+; CHECK: exiting.prol:
+; CHECK-NEXT: switch i16 [[C3:%.*]], label [[DEFAULT_LOOPEXIT_LOOPEXIT1:%.*]] [
+; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT2:%.*]]
+; CHECK-NEXT: i16 95, label [[LATCH_PROL]]
+; CHECK-NEXT: ]
+; CHECK: latch.prol:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_PROL]] = add nuw nsw i64 [[INDVARS_IV_PROL]], 1
+; CHECK-NEXT: [[C2_PROL:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_PROL]], [[C1]]
+; CHECK-NEXT: [[PROL_ITER_SUB]] = sub i64 [[PROL_ITER]], 1
+; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_SUB]], 0
+; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[HEADER_PROL]], label [[HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: header.prol.loopexit.unr-lcssa:
+; CHECK-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[LATCH_PROL]] ]
+; CHECK-NEXT: br label [[HEADER_PROL_LOOPEXIT]]
+; CHECK: header.prol.loopexit:
+; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[PREHEADER:%.*]] ], [ [[INDVARS_IV_UNR_PH]], [[HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 3
+; CHECK-NEXT: br i1 [[TMP1]], label [[LATCHEXIT:%.*]], label [[PREHEADER_NEW:%.*]]
+; CHECK: preheader.new:
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ]
+; CHECK-NEXT: br label [[EXITING:%.*]]
+; CHECK: exiting:
+; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT:%.*]] [
+; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT:%.*]]
+; CHECK-NEXT: i16 95, label [[LATCH:%.*]]
+; CHECK-NEXT: ]
+; CHECK: latch:
+; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: br label [[EXITING_1:%.*]]
+; CHECK: latchexit.unr-lcssa:
+; CHECK-NEXT: br label [[LATCHEXIT]]
+; CHECK: latchexit:
+; CHECK-NEXT: ret void
+; CHECK: default.loopexit.loopexit:
+; CHECK-NEXT: br label [[DEFAULT_LOOPEXIT:%.*]]
+; CHECK: default.loopexit.loopexit1:
+; CHECK-NEXT: br label [[DEFAULT_LOOPEXIT]]
+; CHECK: default.loopexit:
+; CHECK-NEXT: br label [[DEFAULT:%.*]]
+; CHECK: default:
+; CHECK-NEXT: ret void
+; CHECK: otherexit.loopexit:
+; CHECK-NEXT: br label [[OTHEREXIT:%.*]]
+; CHECK: otherexit.loopexit2:
+; CHECK-NEXT: br label [[OTHEREXIT]]
+; CHECK: otherexit:
+; CHECK-NEXT: br label [[DEFAULT]]
+; CHECK: exiting.1:
+; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
+; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]]
+; CHECK-NEXT: i16 95, label [[LATCH_1:%.*]]
+; CHECK-NEXT: ]
+; CHECK: latch.1:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1
+; CHECK-NEXT: br label [[EXITING_2:%.*]]
+; CHECK: exiting.2:
+; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
+; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]]
+; CHECK-NEXT: i16 95, label [[LATCH_2:%.*]]
+; CHECK-NEXT: ]
+; CHECK: latch.2:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1
+; CHECK-NEXT: br label [[EXITING_3:%.*]]
+; CHECK: exiting.3:
+; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
+; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]]
+; CHECK-NEXT: i16 95, label [[LATCH_3]]
+; CHECK-NEXT: ]
+; CHECK: latch.3:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1
+; CHECK-NEXT: [[C2_3:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_3]], [[C1]]
+; CHECK-NEXT: br i1 [[C2_3]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP5:![0-9]+]]
+;
preheader:
%c1 = zext i32 undef to i64
br label %header
@@ -153,8 +345,8 @@ header: ; preds = %latch, %preheader
exiting: ; preds = %header
switch i16 %c3, label %default [
- i16 45, label %otherexit
- i16 95, label %latch
+ i16 45, label %otherexit
+ i16 95, label %latch
]
latch: ; preds = %exiting
@@ -175,17 +367,205 @@ otherexit: ; preds = %exiting
; exit block (%exitB) has an exiting block and another exit block as predecessors.
; exiting block comes from inner loop.
define void @test5(i1 %c) {
-; CHECK-LABEL: test5
-; CHECK-LABEL: bb1:
-; CHECK-NEXT: br i1 false, label %outerH.prol.preheader, label %outerH.prol.loopexit
-
-; CHECK-LABEL: outerH.prol.preheader:
-; CHECK-NEXT: br label %outerH.prol
-
-; CHECK-LABEL: outerH.prol:
-; CHECK-NEXT: %tmp4.prol = phi i32 [ %tmp6.prol, %outerLatch.prol ], [ undef, %outerH.prol.preheader ]
-; CHECK-NEXT: %prol.iter = phi i32 [ 0, %outerH.prol.preheader ], [ %prol.iter.sub, %outerLatch.prol ]
-; CHECK-NEXT: br label %innerH.prol
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP:%.*]] = icmp sgt i32 undef, 79
+; CHECK-NEXT: br i1 [[TMP]], label [[OUTERLATCHEXIT:%.*]], label [[BB1:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: br i1 false, label [[OUTERH_PROL_PREHEADER:%.*]], label [[OUTERH_PROL_LOOPEXIT:%.*]]
+; CHECK: outerH.prol.preheader:
+; CHECK-NEXT: br label [[OUTERH_PROL:%.*]]
+; CHECK: outerH.prol:
+; CHECK-NEXT: [[TMP4_PROL:%.*]] = phi i32 [ [[TMP6_PROL:%.*]], [[OUTERLATCH_PROL:%.*]] ], [ undef, [[OUTERH_PROL_PREHEADER]] ]
+; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i32 [ 0, [[OUTERH_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[OUTERLATCH_PROL]] ]
+; CHECK-NEXT: br label [[INNERH_PROL:%.*]]
+; CHECK: innerH.prol:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[INNEREXITING_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1:%.*]]
+; CHECK: innerexiting.prol:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2:%.*]]
+; CHECK: innerLatch.prol:
+; CHECK-NEXT: br i1 false, label [[INNERH_1_PROL:%.*]], label [[OUTERLATCH_PROL]]
+; CHECK: innerH.1.prol:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_1_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]]
+; CHECK: innerexiting.1.prol:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_1_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]]
+; CHECK: innerLatch.1.prol:
+; CHECK-NEXT: br i1 false, label [[INNERH_2_PROL:%.*]], label [[OUTERLATCH_PROL]]
+; CHECK: innerH.2.prol:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_2_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]]
+; CHECK: innerexiting.2.prol:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_2_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]]
+; CHECK: innerLatch.2.prol:
+; CHECK-NEXT: br i1 false, label [[INNERH_3_PROL:%.*]], label [[OUTERLATCH_PROL]]
+; CHECK: innerH.3.prol:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_3_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]]
+; CHECK: innerexiting.3.prol:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_3_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]]
+; CHECK: innerLatch.3.prol:
+; CHECK-NEXT: br i1 false, label [[INNERH_PROL]], label [[OUTERLATCH_PROL]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: outerLatch.prol:
+; CHECK-NEXT: [[TMP6_PROL]] = add i32 [[TMP4_PROL]], 1
+; CHECK-NEXT: [[TMP7_PROL:%.*]] = icmp sgt i32 [[TMP6_PROL]], 79
+; CHECK-NEXT: [[PROL_ITER_SUB]] = sub i32 [[PROL_ITER]], 1
+; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i32 [[PROL_ITER_SUB]], 0
+; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[OUTERH_PROL]], label [[OUTERH_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK: outerH.prol.loopexit.unr-lcssa:
+; CHECK-NEXT: [[TMP4_UNR_PH:%.*]] = phi i32 [ [[TMP6_PROL]], [[OUTERLATCH_PROL]] ]
+; CHECK-NEXT: br label [[OUTERH_PROL_LOOPEXIT]]
+; CHECK: outerH.prol.loopexit:
+; CHECK-NEXT: [[TMP4_UNR:%.*]] = phi i32 [ undef, [[BB1]] ], [ [[TMP4_UNR_PH]], [[OUTERH_PROL_LOOPEXIT_UNR_LCSSA]] ]
+; CHECK-NEXT: br i1 false, label [[OUTERLATCHEXIT_LOOPEXIT:%.*]], label [[BB1_NEW:%.*]]
+; CHECK: bb1.new:
+; CHECK-NEXT: br label [[OUTERH:%.*]]
+; CHECK: outerH:
+; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP4_UNR]], [[BB1_NEW]] ], [ [[TMP6_3:%.*]], [[OUTERLATCH_3:%.*]] ]
+; CHECK-NEXT: br label [[INNERH:%.*]]
+; CHECK: innerH:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT:%.*]]
+; CHECK: innerexiting:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT:%.*]]
+; CHECK: innerLatch:
+; CHECK-NEXT: br i1 false, label [[INNERH_1:%.*]], label [[OUTERLATCH:%.*]]
+; CHECK: outerLatch:
+; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP4]], 1
+; CHECK-NEXT: br label [[INNERH_13:%.*]]
+; CHECK: outerLatchExit.loopexit.unr-lcssa:
+; CHECK-NEXT: br label [[OUTERLATCHEXIT_LOOPEXIT]]
+; CHECK: outerLatchExit.loopexit:
+; CHECK-NEXT: br label [[OUTERLATCHEXIT]]
+; CHECK: outerLatchExit:
+; CHECK-NEXT: ret void
+; CHECK: exitB.loopexit.loopexit.loopexit:
+; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT:%.*]]
+; CHECK: exitB.loopexit.loopexit.loopexit13:
+; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT]]
+; CHECK: exitB.loopexit.loopexit.loopexit15:
+; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT]]
+; CHECK: exitB.loopexit.loopexit.loopexit17:
+; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT]]
+; CHECK: exitB.loopexit.loopexit:
+; CHECK-NEXT: br label [[EXITB_LOOPEXIT:%.*]]
+; CHECK: exitB.loopexit.loopexit2:
+; CHECK-NEXT: br label [[EXITB_LOOPEXIT]]
+; CHECK: exitB.loopexit:
+; CHECK-NEXT: br label [[EXITB:%.*]]
+; CHECK: exitB:
+; CHECK-NEXT: ret void
+; CHECK: otherexitB.loopexit.loopexit:
+; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT:%.*]]
+; CHECK: otherexitB.loopexit.loopexit12:
+; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT]]
+; CHECK: otherexitB.loopexit.loopexit14:
+; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT]]
+; CHECK: otherexitB.loopexit.loopexit16:
+; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT]]
+; CHECK: otherexitB.loopexit:
+; CHECK-NEXT: br label [[OTHEREXITB:%.*]]
+; CHECK: otherexitB.loopexit1:
+; CHECK-NEXT: br label [[OTHEREXITB]]
+; CHECK: otherexitB:
+; CHECK-NEXT: br label [[EXITB]]
+; CHECK: innerH.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]]
+; CHECK: innerexiting.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]]
+; CHECK: innerLatch.1:
+; CHECK-NEXT: br i1 false, label [[INNERH_2:%.*]], label [[OUTERLATCH]]
+; CHECK: innerH.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]]
+; CHECK: innerexiting.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]]
+; CHECK: innerLatch.2:
+; CHECK-NEXT: br i1 false, label [[INNERH_3:%.*]], label [[OUTERLATCH]]
+; CHECK: innerH.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]]
+; CHECK: innerexiting.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]]
+; CHECK: innerLatch.3:
+; CHECK-NEXT: br i1 false, label [[INNERH]], label [[OUTERLATCH]], !llvm.loop [[LOOP6]]
+; CHECK: innerH.13:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_14:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12:%.*]]
+; CHECK: innerexiting.14:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_15:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13:%.*]]
+; CHECK: innerLatch.15:
+; CHECK-NEXT: br i1 false, label [[INNERH_1_1:%.*]], label [[OUTERLATCH_1:%.*]]
+; CHECK: innerH.1.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_1_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12]]
+; CHECK: innerexiting.1.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_1_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13]]
+; CHECK: innerLatch.1.1:
+; CHECK-NEXT: br i1 false, label [[INNERH_2_1:%.*]], label [[OUTERLATCH_1]]
+; CHECK: innerH.2.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_2_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12]]
+; CHECK: innerexiting.2.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_2_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13]]
+; CHECK: innerLatch.2.1:
+; CHECK-NEXT: br i1 false, label [[INNERH_3_1:%.*]], label [[OUTERLATCH_1]]
+; CHECK: innerH.3.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_3_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12]]
+; CHECK: innerexiting.3.1:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_3_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13]]
+; CHECK: innerLatch.3.1:
+; CHECK-NEXT: br i1 false, label [[INNERH_13]], label [[OUTERLATCH_1]], !llvm.loop [[LOOP6]]
+; CHECK: outerLatch.1:
+; CHECK-NEXT: [[TMP6_1:%.*]] = add i32 [[TMP6]], 1
+; CHECK-NEXT: br label [[INNERH_26:%.*]]
+; CHECK: innerH.26:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_27:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14:%.*]]
+; CHECK: innerexiting.27:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_28:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15:%.*]]
+; CHECK: innerLatch.28:
+; CHECK-NEXT: br i1 false, label [[INNERH_1_2:%.*]], label [[OUTERLATCH_2:%.*]]
+; CHECK: innerH.1.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_1_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14]]
+; CHECK: innerexiting.1.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_1_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15]]
+; CHECK: innerLatch.1.2:
+; CHECK-NEXT: br i1 false, label [[INNERH_2_2:%.*]], label [[OUTERLATCH_2]]
+; CHECK: innerH.2.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_2_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14]]
+; CHECK: innerexiting.2.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_2_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15]]
+; CHECK: innerLatch.2.2:
+; CHECK-NEXT: br i1 false, label [[INNERH_3_2:%.*]], label [[OUTERLATCH_2]]
+; CHECK: innerH.3.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_3_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14]]
+; CHECK: innerexiting.3.2:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_3_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15]]
+; CHECK: innerLatch.3.2:
+; CHECK-NEXT: br i1 false, label [[INNERH_26]], label [[OUTERLATCH_2]], !llvm.loop [[LOOP6]]
+; CHECK: outerLatch.2:
+; CHECK-NEXT: [[TMP6_2:%.*]] = add i32 [[TMP6_1]], 1
+; CHECK-NEXT: br label [[INNERH_39:%.*]]
+; CHECK: innerH.39:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_310:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16:%.*]]
+; CHECK: innerexiting.310:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_311:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17:%.*]]
+; CHECK: innerLatch.311:
+; CHECK-NEXT: br i1 false, label [[INNERH_1_3:%.*]], label [[OUTERLATCH_3]]
+; CHECK: innerH.1.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_1_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16]]
+; CHECK: innerexiting.1.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_1_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17]]
+; CHECK: innerLatch.1.3:
+; CHECK-NEXT: br i1 false, label [[INNERH_2_3:%.*]], label [[OUTERLATCH_3]]
+; CHECK: innerH.2.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_2_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16]]
+; CHECK: innerexiting.2.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_2_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17]]
+; CHECK: innerLatch.2.3:
+; CHECK-NEXT: br i1 false, label [[INNERH_3_3:%.*]], label [[OUTERLATCH_3]]
+; CHECK: innerH.3.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNEREXITING_3_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16]]
+; CHECK: innerexiting.3.3:
+; CHECK-NEXT: br i1 [[C]], label [[INNERLATCH_3_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17]]
+; CHECK: innerLatch.3.3:
+; CHECK-NEXT: br i1 false, label [[INNERH_39]], label [[OUTERLATCH_3]], !llvm.loop [[LOOP6]]
+; CHECK: outerLatch.3:
+; CHECK-NEXT: [[TMP6_3]] = add i32 [[TMP6_2]], 1
+; CHECK-NEXT: [[TMP7_3:%.*]] = icmp sgt i32 [[TMP6_3]], 79
+; CHECK-NEXT: br i1 [[TMP7_3]], label [[OUTERLATCHEXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[OUTERH]], !llvm.loop [[LOOP8:![0-9]+]]
+;
bb:
%tmp = icmp sgt i32 undef, 79
br i1 %tmp, label %outerLatchExit, label %bb1
@@ -226,27 +606,70 @@ otherexitB: ; preds = %innerH
; Blocks reachable from exits (not_zero44) have the IDom as the block within the loop (Header).
; Update the IDom to the preheader.
define void @test6(i1 %c) {
-; CHECK-LABEL: test6
-; CHECK-LABEL: header.prol.preheader:
-; CHECK-NEXT: br label %header.prol
-
-; CHECK-LABEL: header.prol:
-; CHECK-NEXT: %indvars.iv.prol = phi i64 [ undef, %header.prol.preheader ], [ %indvars.iv.next.prol, %latch.prol ]
-; CHECK-NEXT: %prol.iter = phi i64 [ %xtraiter, %header.prol.preheader ], [ %prol.iter.sub, %latch.prol ]
-
-; CHECK-NEXT: br i1 %c, label %latch.prol, label %otherexit.loopexit1
-
-; CHECK-LABEL: header.prol.loopexit.unr-lcssa:
-; CHECK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.prol, %latch.prol ]
-; CHECK-NEXT: br label %header.prol.loopexit
-
-; CHECK-LABEL: header.prol.loopexit:
-; CHECK-NEXT: %indvars.iv.unr = phi i64 [ undef, %entry ], [ %indvars.iv.unr.ph, %header.prol.loopexit.unr-lcssa ]
-; CHECK-NEXT: %5 = icmp ult i64 %2, 3
-; CHECK-NEXT: br i1 %5, label %latchexit, label %entry.new
-
-; CHECK-LABEL: entry.new:
-; CHECK-NEXT: br label %header
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 undef, i64 616)
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[SMAX]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], undef
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[TMP2]], 1
+; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP3]], 3
+; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
+; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[HEADER_PROL_PREHEADER:%.*]], label [[HEADER_PROL_LOOPEXIT:%.*]]
+; CHECK: header.prol.preheader:
+; CHECK-NEXT: br label [[HEADER_PROL:%.*]]
+; CHECK: header.prol:
+; CHECK-NEXT: [[INDVARS_IV_PROL:%.*]] = phi i64 [ undef, [[HEADER_PROL_PREHEADER]] ], [ [[INDVARS_IV_NEXT_PROL:%.*]], [[LATCH_PROL:%.*]] ]
+; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ [[XTRAITER]], [[HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[LATCH_PROL]] ]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[LATCH_PROL]], label [[OTHEREXIT_LOOPEXIT1:%.*]]
+; CHECK: latch.prol:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_PROL]] = add nsw i64 [[INDVARS_IV_PROL]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_PROL]], 616
+; CHECK-NEXT: [[PROL_ITER_SUB]] = sub i64 [[PROL_ITER]], 1
+; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_SUB]], 0
+; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[HEADER_PROL]], label [[HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK: header.prol.loopexit.unr-lcssa:
+; CHECK-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[LATCH_PROL]] ]
+; CHECK-NEXT: br label [[HEADER_PROL_LOOPEXIT]]
+; CHECK: header.prol.loopexit:
+; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ undef, [[ENTRY:%.*]] ], [ [[INDVARS_IV_UNR_PH]], [[HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i64 [[TMP2]], 3
+; CHECK-NEXT: br i1 [[TMP5]], label [[LATCHEXIT:%.*]], label [[ENTRY_NEW:%.*]]
+; CHECK: entry.new:
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[ENTRY_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ]
+; CHECK-NEXT: br i1 [[C]], label [[LATCH:%.*]], label [[OTHEREXIT_LOOPEXIT:%.*]]
+; CHECK: latch:
+; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nsw i64 [[INDVARS_IV]], 2
+; CHECK-NEXT: br i1 [[C]], label [[LATCH_1:%.*]], label [[OTHEREXIT_LOOPEXIT]]
+; CHECK: latchexit.unr-lcssa:
+; CHECK-NEXT: br label [[LATCHEXIT]]
+; CHECK: latchexit:
+; CHECK-NEXT: br label [[LATCHEXITSUCC:%.*]]
+; CHECK: otherexit.loopexit:
+; CHECK-NEXT: br label [[OTHEREXIT:%.*]]
+; CHECK: otherexit.loopexit1:
+; CHECK-NEXT: br label [[OTHEREXIT]]
+; CHECK: otherexit:
+; CHECK-NEXT: br label [[OTHEREXITSUCC:%.*]]
+; CHECK: otherexitsucc:
+; CHECK-NEXT: br label [[NOT_ZERO44:%.*]]
+; CHECK: not_zero44:
+; CHECK-NEXT: unreachable
+; CHECK: latchexitsucc:
+; CHECK-NEXT: br label [[NOT_ZERO44]]
+; CHECK: latch.1:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nsw i64 [[INDVARS_IV_NEXT]], 2
+; CHECK-NEXT: br i1 [[C]], label [[LATCH_2:%.*]], label [[OTHEREXIT_LOOPEXIT]]
+; CHECK: latch.2:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nsw i64 [[INDVARS_IV_NEXT_1]], 2
+; CHECK-NEXT: br i1 [[C]], label [[LATCH_3]], label [[OTHEREXIT_LOOPEXIT]]
+; CHECK: latch.3:
+; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nsw i64 [[INDVARS_IV_NEXT_2]], 2
+; CHECK-NEXT: [[TMP6:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_3]], 616
+; CHECK-NEXT: br i1 [[TMP6]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP10:![0-9]+]]
+;
entry:
br label %header
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