[llvm] 9132299 - [LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-06-29T11:00:11-07:00
New Revision: 913229983633cd4c19b9e5534018f9a42e274b30

URL: https://github.com/llvm/llvm-project/commit/913229983633cd4c19b9e5534018f9a42e274b30
DIFF: https://github.com/llvm/llvm-project/commit/913229983633cd4c19b9e5534018f9a42e274b30.diff

LOG: [LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.

We were trying to expand these if they were going to be expanded
in op legalization so that we generated the minimum number of
operations. We failed to take into account that NVT could be
promoted to another legal type in op legalization.

Hoping this fixes the issue on the VE target reported as a follow
up to D96681. The check line changes were taken from before
1e46b6f4012399a2fef5fbbb4ed06fc919835414 so this patch does
appear to improve some cases that had previously regressed.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/test/CodeGen/VE/Scalar/bitreverse.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 997cc39d709ae..27bc2d8c05f7f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -465,7 +465,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
   // If we expand later we'll end up with more operations since we lost the
   // original type. We only do this for scalars since we have a shuffle
   // based lowering for vectors in LegalizeVectorOps.
-  if (!OVT.isVector() && !TLI.isOperationLegalOrCustom(ISD::BSWAP, NVT)) {
+  if (!OVT.isVector() &&
+      !TLI.isOperationLegalOrCustomOrPromote(ISD::BSWAP, NVT)) {
     if (SDValue Res = TLI.expandBSWAP(N, DAG))
       return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
   }
@@ -487,7 +488,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
   // original type. We only do this for scalars since we have a shuffle
   // based lowering for vectors in LegalizeVectorOps.
   if (!OVT.isVector() && OVT.isSimple() &&
-      !TLI.isOperationLegalOrCustom(ISD::BITREVERSE, NVT)) {
+      !TLI.isOperationLegalOrCustomOrPromote(ISD::BITREVERSE, NVT)) {
     if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
       return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
   }

diff  --git a/llvm/test/CodeGen/VE/Scalar/bitreverse.ll b/llvm/test/CodeGen/VE/Scalar/bitreverse.ll
index cceca6824adb4..208c207ff5139 100644
--- a/llvm/test/CodeGen/VE/Scalar/bitreverse.ll
+++ b/llvm/test/CodeGen/VE/Scalar/bitreverse.ll
@@ -49,9 +49,9 @@ define zeroext i32 @func32z(i32 zeroext %p) {
 define signext i16 @func16s(i16 signext %p) {
 ; CHECK-LABEL: func16s:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    bswp %s0, %s0, 1
-; CHECK-NEXT:    and %s0, %s0, (32)0
-; CHECK-NEXT:    srl %s1, %s0, 12
+; CHECK-NEXT:    brv %s0, %s0
+; CHECK-NEXT:    sra.l %s0, %s0, 48
+; CHECK-NEXT:    b.l.t (, %s10)
   %r = tail call i16 @llvm.bitreverse.i16(i16 %p)
   ret i16 %r
 }
@@ -59,9 +59,9 @@ define signext i16 @func16s(i16 signext %p) {
 define zeroext i16 @func16z(i16 zeroext %p) {
 ; CHECK-LABEL: func16z:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    bswp %s0, %s0, 1
-; CHECK-NEXT:    and %s0, %s0, (32)0
-; CHECK-NEXT:    srl %s1, %s0, 12
+; CHECK-NEXT:    brv %s0, %s0
+; CHECK-NEXT:    srl %s0, %s0, 48
+; CHECK-NEXT:    b.l.t (, %s10)
   %r = tail call i16 @llvm.bitreverse.i16(i16 %p)
   ret i16 %r
 }
@@ -69,6 +69,9 @@ define zeroext i16 @func16z(i16 zeroext %p) {
 define signext i8 @func8s(i8 signext %p) {
 ; CHECK-LABEL: func8s:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    brv %s0, %s0
+; CHECK-NEXT:    sra.l %s0, %s0, 56
+; CHECK-NEXT:    b.l.t (, %s10)
   %r = tail call i8 @llvm.bitreverse.i8(i8 %p)
   ret i8 %r
 }
@@ -76,6 +79,9 @@ define signext i8 @func8s(i8 signext %p) {
 define zeroext i8 @func8z(i8 zeroext %p) {
 ; CHECK-LABEL: func8z:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    brv %s0, %s0
+; CHECK-NEXT:    srl %s0, %s0, 56
+; CHECK-NEXT:    b.l.t (, %s10)
   %r = tail call i8 @llvm.bitreverse.i8(i8 %p)
   ret i8 %r
 }