[PATCH] D105130: [RISCV] Enable interleaved access vectorization

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Please upload patches with full context using -U999999 has documented here https://releases.llvm.org/11.0.0/docs/Phabricator.html#requesting-a-review-via-the-web-interface

Do you plan to map these to segment load/store instructions in the future?



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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll:4
+; RUN:   -loop-vectorize -instcombine -force-vector-width=4 \
+; RUN:   -force-vector-interleave=1 -enable-interleaved-mem-accesses=true \
+; RUN:   -runtime-memory-check-threshold=24 < %s | FileCheck %s
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Is `-enable-interleaved-mem-accesses=true` needed if TTI enableInterleavedAccessVectorization() returns true


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105130/new/

https://reviews.llvm.org/D105130