[llvm] f0d6c91 - [X86] Add cmov i33 sgt test case

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-06-29T14:36:33+01:00
New Revision: f0d6c9156b129597f2215b4123ebaae8a3eb57a3

URL: https://github.com/llvm/llvm-project/commit/f0d6c9156b129597f2215b4123ebaae8a3eb57a3
DIFF: https://github.com/llvm/llvm-project/commit/f0d6c9156b129597f2215b4123ebaae8a3eb57a3.diff

LOG: [X86] Add cmov i33 sgt test case

Suggested on D101074 - add a 'icmp sgt i64 %0, -2147483649' comparison that can fold to 'icmp sge i64 %0, -2147483648' on D101074 allowing i32 immediate folding

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/cmov.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll
index 1f4d6d8c6ac5..9aaf8eb5463c 100644
--- a/llvm/test/CodeGen/X86/cmov.ll
+++ b/llvm/test/CodeGen/X86/cmov.ll
@@ -198,6 +198,19 @@ define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
   ret i8 %d
 }
 
+define i64 @test8(i64 %0, i64 %1, i64 %2) {
+; CHECK-LABEL: test8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movabsq $-2147483649, %rcx # imm = 0xFFFFFFFF7FFFFFFF
+; CHECK-NEXT:    cmpq %rcx, %rdi
+; CHECK-NEXT:    cmovleq %rdx, %rax
+; CHECK-NEXT:    retq
+  %4 = icmp sgt i64 %0, -2147483649
+  %5 = select i1 %4, i64 %1, i64 %2
+  ret i64 %5
+}
+
 define i32 @smin(i32 %x) {
 ; CHECK-LABEL: smin:
 ; CHECK:       # %bb.0: