[llvm] 9c5ed8d - [Hexagon] Add patterns to load i1
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 28 10:17:46 PDT 2021
Author: Krzysztof Parzyszek
Date: 2021-06-28T12:17:30-05:00
New Revision: 9c5ed8d567924e807a6466b6ad681c8bf395cf58
URL: https://github.com/llvm/llvm-project/commit/9c5ed8d567924e807a6466b6ad681c8bf395cf58
DIFF: https://github.com/llvm/llvm-project/commit/9c5ed8d567924e807a6466b6ad681c8bf395cf58.diff
LOG: [Hexagon] Add patterns to load i1
This fixes https://llvm.org/PR50853
Added:
llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
llvm/test/CodeGen/Hexagon/isel/extload-i1.ll
Modified:
llvm/lib/Target/Hexagon/HexagonPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index f4223b74c9008..cad5ca8ab92ec 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -1948,6 +1948,9 @@ def: Pat<(HexagonAtPcrel I32:$addr),
// --(12) Load -----------------------------------------------------------
//
+def L1toI32: OutPatFrag<(ops node:$Rs), (A2_subri 0, (i32 $Rs))>;
+def L1toI64: OutPatFrag<(ops node:$Rs), (ToSext64 (L1toI32 $Rs))>;
+
def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
}]>;
@@ -2104,11 +2107,17 @@ let AddedComplexity = 20 in {
}
let AddedComplexity = 30 in {
+ // Loads of i1 are loading a byte, and the byte should be either 0 or 1.
+ // It doesn't matter if it's sign- or zero-extended, so use zero-extension
+ // everywhere.
+ defm: Loadxim_pat<sextloadi1, i32, L1toI32, anyimm0, L2_loadrub_io>;
defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>;
+ defm: Loadxim_pat<sextloadi1, i64, L1toI64, anyimm0, L2_loadrub_io>;
+ defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>;
+
defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>;
defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>;
defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>;
- defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>;
defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>;
defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>;
defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>;
@@ -2118,6 +2127,7 @@ let AddedComplexity = 30 in {
}
let AddedComplexity = 60 in {
+ def: Loadxu_pat<extloadi1, i32, anyimm0, L4_loadrub_ur>;
def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>;
def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>;
def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>;
@@ -2126,6 +2136,7 @@ let AddedComplexity = 60 in {
def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>;
def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>;
def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>;
+ def: Loadxu_pat<zextloadi1, i32, anyimm0, L4_loadrub_ur>;
def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>;
def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>;
def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>;
@@ -2140,6 +2151,11 @@ let AddedComplexity = 60 in {
def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>;
def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>;
+ def: Loadxum_pat<sextloadi1, i32, anyimm0, L1toI32, L4_loadrub_ur>;
+ def: Loadxum_pat<extloadi1, i64, anyimm0, ToAext64, L4_loadrub_ur>;
+ def: Loadxum_pat<sextloadi1, i64, anyimm0, L1toI64, L4_loadrub_ur>;
+ def: Loadxum_pat<zextloadi1, i64, anyimm0, ToZext64, L4_loadrub_ur>;
+
def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>;
def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>;
def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>;
@@ -2152,7 +2168,9 @@ let AddedComplexity = 60 in {
}
let AddedComplexity = 40 in {
+ def: Loadxr_shl_pat<extloadi1, i32, L4_loadrub_rr>;
def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>;
+ def: Loadxr_shl_pat<zextloadi1, i32, L4_loadrub_rr>;
def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>;
def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>;
def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>;
@@ -2170,8 +2188,10 @@ let AddedComplexity = 40 in {
}
let AddedComplexity = 20 in {
+ def: Loadxr_add_pat<extloadi1, i32, L4_loadrub_rr>;
def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>;
def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>;
+ def: Loadxr_add_pat<zextloadi1, i32, L4_loadrub_rr>;
def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>;
def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>;
def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>;
@@ -2188,6 +2208,11 @@ let AddedComplexity = 20 in {
}
let AddedComplexity = 40 in {
+ def: Loadxrm_shl_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>;
+ def: Loadxrm_shl_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>;
+ def: Loadxrm_shl_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>;
+ def: Loadxrm_shl_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>;
+
def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>;
def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>;
def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>;
@@ -2199,7 +2224,12 @@ let AddedComplexity = 40 in {
def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>;
}
-let AddedComplexity = 20 in {
+let AddedComplexity = 30 in {
+ def: Loadxrm_add_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>;
+ def: Loadxrm_add_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>;
+ def: Loadxrm_add_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>;
+ def: Loadxrm_add_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>;
+
def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>;
def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>;
def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>;
@@ -2214,12 +2244,13 @@ let AddedComplexity = 20 in {
// Absolute address
let AddedComplexity = 60 in {
+ def: Loada_pat<extloadi1, i32, anyimm0, PS_loadrubabs>;
def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>;
- def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>;
def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>;
+ def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>;
def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>;
- def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>;
def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>;
+ def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>;
def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>;
def: Loada_pat<load, i32, anyimm2, PS_loadriabs>;
def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>;
@@ -2238,6 +2269,12 @@ let AddedComplexity = 60 in {
}
let AddedComplexity = 30 in {
+ def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>;
+ def: Loadam_pat<sextloadi1, i32, anyimm0, L1toI32, PS_loadrubabs>;
+ def: Loadam_pat<extloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>;
+ def: Loadam_pat<sextloadi1, i64, anyimm0, L1toI64, PS_loadrubabs>;
+ def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>;
+
def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>;
def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>;
def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>;
@@ -2247,9 +2284,6 @@ let AddedComplexity = 30 in {
def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>;
def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>;
def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>;
-
- def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>;
- def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>;
}
// GP-relative address
@@ -2280,6 +2314,11 @@ let AddedComplexity = 100 in {
}
let AddedComplexity = 70 in {
+ def: Loadam_pat<sextloadi1, i32, addrgp, L1toI32, L2_loadrubgp>;
+ def: Loadam_pat<extloadi1, i64, addrgp, ToAext64, L2_loadrubgp>;
+ def: Loadam_pat<sextloadi1, i64, addrgp, L1toI64, L2_loadrubgp>;
+ def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>;
+
def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>;
def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>;
def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>;
@@ -2291,17 +2330,8 @@ let AddedComplexity = 70 in {
def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>;
def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
- def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>;
}
-
-// Sign-extending loads of i1 need to replicate the lowest bit throughout
-// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
-// do the trick.
-let AddedComplexity = 20 in
-def: Pat<(i32 (sextloadi1 I32:$Rs)),
- (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
-
// Patterns for loads of i1:
def: Pat<(i1 (load AddrFI:$fi)),
(C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
diff --git a/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll b/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
new file mode 100644
index 0000000000000..7c3f73d098476
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+define i64 @f0(i32 %a0, i64 %a1, i32 %a2, i32 %a3, i1 zeroext %a4) #0 {
+; CHECK-LABEL: f0:
+; CHECK: // %bb.0: // %b0
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r29+#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = asr(r0,#31)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+b0:
+ %v0 = sext i1 %a4 to i64
+ ret i64 %v0
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+v66,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll b/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll
new file mode 100644
index 0000000000000..def04ee4026c1
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll
@@ -0,0 +1,380 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+ at array8 = global [128 x i8] zeroinitializer
+ at array32 = global [128 x i32] zeroinitializer
+ at global_gp = global i1 false
+
+; Sign extensions
+
+define i32 @f0(i1* %a0) #0 {
+; CHECK-LABEL: f0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0+#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 1
+ %v1 = load i1, i1* %v0
+ %v2 = sext i1 %v1 to i32
+ ret i32 %v2
+}
+
+define i32 @f1(i1* %a0, i32 %a1) #0 {
+; CHECK-LABEL: f1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0+r1<<#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 %a1
+ %v1 = load i1, i1* %v0
+ %v2 = sext i1 %v1 to i32
+ ret i32 %v2
+}
+
+define i32 @f2(i32 %a0) #0 {
+; CHECK-LABEL: f2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0+##array8)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i8], [128 x i8]* @array8, i32 0, i32 %a0
+ %v1 = bitcast i8* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = sext i1 %v2 to i32
+ ret i32 %v3
+}
+
+define i32 @f3(i32 %a0) #0 {
+; CHECK-LABEL: f3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0<<#2+##array32)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i32], [128 x i32]* @array32, i32 0, i32 %a0
+ %v1 = bitcast i32* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = sext i1 %v2 to i32
+ ret i32 %v3
+}
+
+define i32 @f4() #0 {
+; CHECK-LABEL: f4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(gp+#global_gp)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = load i1, i1* @global_gp
+ %v1 = sext i1 %v0 to i32
+ ret i32 %v1
+}
+
+define i32 @f5(i64 %a0, i64 %a1, i64 %a2, i1 signext %a3) #0 {
+; CHECK-LABEL: f5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r29+#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = sext i1 %a3 to i32
+ ret i32 %v0
+}
+
+define i64 @f6(i1* %a0) #0 {
+; CHECK-LABEL: f6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0+#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = asr(r0,#31)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 1
+ %v1 = load i1, i1* %v0
+ %v2 = sext i1 %v1 to i64
+ ret i64 %v2
+}
+
+define i64 @f7(i1* %a0, i32 %a1) #0 {
+; CHECK-LABEL: f7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0+r1<<#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = asr(r0,#31)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 %a1
+ %v1 = load i1, i1* %v0
+ %v2 = sext i1 %v1 to i64
+ ret i64 %v2
+}
+
+define i64 @f8(i32 %a0) #0 {
+; CHECK-LABEL: f8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0+##array8)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = asr(r0,#31)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i8], [128 x i8]* @array8, i32 0, i32 %a0
+ %v1 = bitcast i8* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = sext i1 %v2 to i64
+ ret i64 %v3
+}
+
+define i64 @f9(i32 %a0) #0 {
+; CHECK-LABEL: f9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0<<#2+##array32)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = asr(r0,#31)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i32], [128 x i32]* @array32, i32 0, i32 %a0
+ %v1 = bitcast i32* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = sext i1 %v2 to i64
+ ret i64 %v3
+}
+
+define i64 @f10() #0 {
+; CHECK-LABEL: f10:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(gp+#global_gp)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = asr(r0,#31)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = load i1, i1* @global_gp
+ %v1 = sext i1 %v0 to i64
+ ret i64 %v1
+}
+
+define i64 @f11(i64 %a0, i64 %a1, i64 %a2, i1 signext %a3) #0 {
+; CHECK-LABEL: f11:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r29+#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = sub(#0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = asr(r0,#31)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = sext i1 %a3 to i64
+ ret i64 %v0
+}
+
+; Zero-extensions
+
+define i32 @f12(i1* %a0) #0 {
+; CHECK-LABEL: f12:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memub(r0+#1)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 1
+ %v1 = load i1, i1* %v0
+ %v2 = zext i1 %v1 to i32
+ ret i32 %v2
+}
+
+define i32 @f13(i1* %a0, i32 %a1) #0 {
+; CHECK-LABEL: f13:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r0+r1<<#0)
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 %a1
+ %v1 = load i1, i1* %v0
+ %v2 = zext i1 %v1 to i32
+ ret i32 %v2
+}
+
+define i32 @f14(i32 %a0) #0 {
+; CHECK-LABEL: f14:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r0+##array8)
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i8], [128 x i8]* @array8, i32 0, i32 %a0
+ %v1 = bitcast i8* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = zext i1 %v2 to i32
+ ret i32 %v3
+}
+
+define i32 @f15(i32 %a0) #0 {
+; CHECK-LABEL: f15:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r0<<#2+##array32)
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i32], [128 x i32]* @array32, i32 0, i32 %a0
+ %v1 = bitcast i32* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = zext i1 %v2 to i32
+ ret i32 %v3
+}
+
+define i32 @f16() #0 {
+; CHECK-LABEL: f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(gp+#global_gp)
+; CHECK-NEXT: }
+ %v0 = load i1, i1* @global_gp
+ %v1 = zext i1 %v0 to i32
+ ret i32 %v1
+}
+
+define i32 @f17(i64 %a0, i64 %a1, i64 %a2, i1 zeroext %a3) #0 {
+; CHECK-LABEL: f17:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r29+#0)
+; CHECK-NEXT: }
+ %v0 = zext i1 %a3 to i32
+ ret i32 %v0
+}
+
+define i64 @f18(i1* %a0) #0 {
+; CHECK-LABEL: f18:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r1 = #0
+; CHECK-NEXT: r0 = memub(r0+#1)
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 1
+ %v1 = load i1, i1* %v0
+ %v2 = zext i1 %v1 to i64
+ ret i64 %v2
+}
+
+define i64 @f19(i1* %a0, i32 %a1) #0 {
+; CHECK-LABEL: f19:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = #0
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r0+r1<<#0)
+; CHECK-NEXT: }
+ %v0 = getelementptr i1, i1* %a0, i32 %a1
+ %v1 = load i1, i1* %v0
+ %v2 = zext i1 %v1 to i64
+ ret i64 %v2
+}
+
+define i64 @f20(i32 %a0) #0 {
+; CHECK-LABEL: f20:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = #0
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r0+##array8)
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i8], [128 x i8]* @array8, i32 0, i32 %a0
+ %v1 = bitcast i8* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = zext i1 %v2 to i64
+ ret i64 %v3
+}
+
+define i64 @f21(i32 %a0) #0 {
+; CHECK-LABEL: f21:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = #0
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r0<<#2+##array32)
+; CHECK-NEXT: }
+ %v0 = getelementptr [128 x i32], [128 x i32]* @array32, i32 0, i32 %a0
+ %v1 = bitcast i32* %v0 to i1*
+ %v2 = load i1, i1* %v1
+ %v3 = zext i1 %v2 to i64
+ ret i64 %v3
+}
+
+define i64 @f22() #0 {
+; CHECK-LABEL: f22:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = #0
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(gp+#global_gp)
+; CHECK-NEXT: }
+ %v0 = load i1, i1* @global_gp
+ %v1 = zext i1 %v0 to i64
+ ret i64 %v1
+}
+
+define i64 @f23(i64 %a0, i64 %a1, i64 %a2, i1 signext %a3) #0 {
+; CHECK-LABEL: f23:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r1 = #0
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: r0 = memub(r29+#0)
+; CHECK-NEXT: }
+ %v0 = zext i1 %a3 to i64
+ ret i64 %v0
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv66" }
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