[llvm] 75cacc6 - [AMDGPU] Use opName instead of PseudoName in VOP2 multiclasses. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-06-28T16:46:35+01:00
New Revision: 75cacc6775ad8fc3d89c89ff77fc4a3b7de32111

URL: https://github.com/llvm/llvm-project/commit/75cacc6775ad8fc3d89c89ff77fc4a3b7de32111
DIFF: https://github.com/llvm/llvm-project/commit/75cacc6775ad8fc3d89c89ff77fc4a3b7de32111.diff

LOG: [AMDGPU] Use opName instead of PseudoName in VOP2 multiclasses. NFC.

This is just for consistency with all other instruction multiclasses
that pass around pseudo names as arguments.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOP2Instructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 6ad23bc7497a..6c58769316cb 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1278,20 +1278,20 @@ let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
       VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
       VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
   }
-  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
+  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string opName = NAME> {
     def _e32_gfx6_gfx7 :
-      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
-      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
+      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.SI>,
+      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl>;
   }
-  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
+  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> {
     def _e64_gfx6_gfx7 :
-      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
-      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
+      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>,
+      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;
   }
-  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
+  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> {
     def _e64_gfx6_gfx7 :
-      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
-      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
+      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>,
+      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;
   }
 } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
 
@@ -1308,16 +1308,16 @@ multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
   VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
 
 multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
-  string PseudoName, string asmName>  {
-  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
-  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
+  string opName, string asmName>  {
+  defvar ps32 = !cast<VOP2_Pseudo>(opName#"_e32");
+  defvar ps64 = !cast<VOP3_Pseudo>(opName#"_e64");
 
   let AsmString = asmName # ps32.AsmOperands in {
-    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
+    defm "" : VOP2_Real_e32_gfx6_gfx7<op, opName>;
   }
 
    let AsmString = asmName # ps64.AsmOperands in {
-    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
+    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, opName>;
   }
 }