[PATCH] D104394: [MachineCopyPropagation] Fix differences in code gen when compiling with -g

[Alexandru Octavian Buțiu via Phabricator via llvm-commits]

predator5047 updated this revision to Diff 354833.
predator5047 added a comment.

Update debug instructions if a register is changed because of backward propagation.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104394/new/

https://reviews.llvm.org/D104394

Files:
  llvm/lib/CodeGen/MachineCopyPropagation.cpp
  llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir


Index: llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir
@@ -0,0 +1,20 @@
+# RUN: llc -mtriple=i686-- -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
+
+
+---
+# Test that machine copy propagation ignores DBG_VALUE and DBL_VALUE_LIST and updates it.
+# CHECK-LABEL: name: foo
+# CHECK: bb.0:
+# CHECK-NEXT: $rax = MOV64ri 31
+# CHECK-NEXT: DBG_VALUE $rax
+# CHECK-NEXT: DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rax, 0, 0
+# CHECK-NEXT: RETQ implicit killed $rax
+name: foo
+body: |
+  bb.0:
+    renamable $rcx = MOV64ri 31
+    DBG_VALUE $rcx, 0, 0, 0, 0
+    DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rcx, 0, 0
+    $rax = COPY killed renamable $rcx
+    RETQ implicit killed $rax
+...
Index: llvm/lib/CodeGen/MachineCopyPropagation.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -826,6 +826,7 @@
     MachineBasicBlock &MBB) {
   LLVM_DEBUG(dbgs() << "MCP: BackwardCopyPropagateBlock " << MBB.getName()
                     << "\n");
+  llvm::DenseMap<llvm::MCRegister, llvm::MachineInstr *> RegToCopies;
 
   for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
        I != E;) {
@@ -846,6 +847,10 @@
         Tracker.invalidateRegister(Src, *TRI);
         Tracker.invalidateRegister(Def, *TRI);
         Tracker.trackCopy(MI, *TRI);
+        // Map registers to copy instructions.
+        for (MCRegUnitIterator RUI(Src, TRI); RUI.isValid(); ++RUI) {
+          RegToCopies[*RUI] = MI;
+        }
         continue;
       }
     }
@@ -870,12 +875,31 @@
       if (MO.isDef())
         Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI);
 
-      if (MO.readsReg())
+      if (MO.readsReg() && MO.isDebug()) {
+        //  Check if the register in the debug instruction is utilized
+        // in a copy instruction, so we can update the debug info if the
+        // register is changed.
+        for (MCRegUnitIterator RUI(MO.getReg().asMCReg(), TRI); RUI.isValid();
+             ++RUI) {
+          auto MIIT = RegToCopies.find(*RUI);
+          if (MIIT != RegToCopies.end()) {
+            CopyDbgUsers[MIIT->second].insert(MI);
+          }
+        }
+      } else if (MO.readsReg()) {
         Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI);
+      }
     }
   }
 
   for (auto *Copy : MaybeDeadCopies) {
+
+    Register NewR = Copy->getOperand(1).getReg();
+    Register OldR = Copy->getOperand(0).getReg();
+    SmallVector<MachineInstr *> MaybeDeadDbgUsers(CopyDbgUsers[Copy].begin(),
+                                                  CopyDbgUsers[Copy].end());
+
+    MRI->updateDbgUsersToReg(NewR.asMCReg(), OldR.asMCReg(), MaybeDeadDbgUsers);
     Copy->eraseFromParent();
     ++NumDeletes;
   }


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