[PATCH] D104874: [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for fp constants

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

I do not actually think we can fix or at least easily fix rematerialization itself when we have subregs, something like this:

  undef %25.sub1:sreg_64 = S_MOV_B32 1056702873
  %25.sub0:sreg_64 = S_MOV_B32 2093606576

Moving a first instruction will leave a second one with %25 use without a def. We would need to always move all defs and that hardly counts as trivially rematerializable, especially if we have multiple defs.

Although that seems to be possible to improve this and combine individual 32 bit moves into this pseudo inside the RA pipeline, after coalescer and right before the pre-RA scheduler. That way greedy will see a single instruction, but we also allow coalescer to work. This should remove the heuristic aspect of it, although will need a new pass and SReg_64 defs scan.


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  https://reviews.llvm.org/D104874/new/

https://reviews.llvm.org/D104874