[PATCH] D104874: [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for fp constants

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

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This is to allow 64 bit constant rematerialization. If a constant
is split into two separate moves initializing sub0 and sub1 like
now RA cannot rematerizalize a 64 bit register.

This is a heuristic. There are pros and cons in using a wide 64 bit
move vs splitting it into two move instructions. If an immediate will
stay as a whole it can be rematerialized and folded. If it is split
it can be better coalesced and its parts can be folded.

Do this only for f64 in the assumption that an f64 value rarely used
as halfs but rather in fp64 instructions as a whole register.

As this is a heuristic there are some minor regressions, but the
overall impact is positive. This gives 10-20% uplift in a set of
huge apps heavily using double precession math.

Fixes: SWDEV-292645


https://reviews.llvm.org/D104874

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
  llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
  llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
  llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll
  llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll

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