[llvm] 4e22c72 - [PowerPC] Disable combine 64-bit bswap(load) without LDBRX

[Nemanja Ivanovic via llvm-commits]

Author: Nemanja Ivanovic
Date: 2021-06-25T15:11:22-05:00
New Revision: 4e22c7265d86419f15f9edab5e0ebf2b55aa4295

URL: https://github.com/llvm/llvm-project/commit/4e22c7265d86419f15f9edab5e0ebf2b55aa4295
DIFF: https://github.com/llvm/llvm-project/commit/4e22c7265d86419f15f9edab5e0ebf2b55aa4295.diff

LOG: [PowerPC] Disable combine 64-bit bswap(load) without LDBRX

This causes failures on the big endian bootstrap bot.
Disabling this combine temporarily until I can get a proper fix.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/test/CodeGen/PowerPC/bswap-load-store.ll
    llvm/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f2bc01bc6d9e..4a60531f86d5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15251,7 +15251,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
     LoadSDNode *LD = cast<LoadSDNode>(N->getOperand(0));
 
     // Can't split volatile or atomic loads.
-    if (!LD->isSimple())
+    // FIXME: Disabling this to unblock the big endian bot until I can get it
+    // fixed.
+    if (!LD->isSimple() || !Subtarget.hasLDBRX())
       return SDValue();
     SDValue BasePtr = LD->getBasePtr();
     SDValue Lo = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr,

diff  --git a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
index 0c9b7a709451..c85bb542267a 100644
--- a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
+++ b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
@@ -151,12 +151,19 @@ define i64 @LDBRX(i8* %ptr, i64 %off) {
 ;
 ; X64-LABEL: LDBRX:
 ; X64:       # %bb.0:
-; X64-NEXT:    li r6, 4
-; X64-NEXT:    lwbrx r5, r3, r4
-; X64-NEXT:    add r3, r3, r4
-; X64-NEXT:    lwbrx r3, r3, r6
-; X64-NEXT:    rldimi r5, r3, 32, 0
-; X64-NEXT:    mr r3, r5
+; X64-NEXT:    ldx r4, r3, r4
+; X64-NEXT:    rotldi r5, r4, 16
+; X64-NEXT:    rotldi r3, r4, 8
+; X64-NEXT:    rldimi r3, r5, 8, 48
+; X64-NEXT:    rotldi r5, r4, 24
+; X64-NEXT:    rldimi r3, r5, 16, 40
+; X64-NEXT:    rotldi r5, r4, 32
+; X64-NEXT:    rldimi r3, r5, 24, 32
+; X64-NEXT:    rotldi r5, r4, 48
+; X64-NEXT:    rldimi r3, r5, 40, 16
+; X64-NEXT:    rotldi r5, r4, 56
+; X64-NEXT:    rldimi r3, r5, 48, 8
+; X64-NEXT:    rldimi r3, r4, 56, 0
 ; X64-NEXT:    blr
 ;
 ; PWR7_64-LABEL: LDBRX:

diff  --git a/llvm/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll b/llvm/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll
index d8889cd7c791..494e0f40b736 100644
--- a/llvm/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll
+++ b/llvm/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll
@@ -4,11 +4,20 @@
 define void @bs(i64* %p) {
 ; CHECK-LABEL: bs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 4
-; CHECK-NEXT:    lwbrx 5, 0, 3
-; CHECK-NEXT:    lwbrx 4, 3, 4
-; CHECK-NEXT:    rldimi 5, 4, 32, 0
-; CHECK-NEXT:    std 5, 0(3)
+; CHECK-NEXT:    ld 4, 0(3)
+; CHECK-NEXT:    rotldi 5, 4, 16
+; CHECK-NEXT:    rotldi 6, 4, 8
+; CHECK-NEXT:    rldimi 6, 5, 8, 48
+; CHECK-NEXT:    rotldi 5, 4, 24
+; CHECK-NEXT:    rldimi 6, 5, 16, 40
+; CHECK-NEXT:    rotldi 5, 4, 32
+; CHECK-NEXT:    rldimi 6, 5, 24, 32
+; CHECK-NEXT:    rotldi 5, 4, 48
+; CHECK-NEXT:    rldimi 6, 5, 40, 16
+; CHECK-NEXT:    rotldi 5, 4, 56
+; CHECK-NEXT:    rldimi 6, 5, 48, 8
+; CHECK-NEXT:    rldimi 6, 4, 56, 0
+; CHECK-NEXT:    std 6, 0(3)
 ; CHECK-NEXT:    blr
   %x = load i64, i64* %p, align 8
   %b = call i64 @llvm.bswap.i64(i64 %x)
@@ -41,10 +50,19 @@ define i64 @volatile_ld(i64* %p) {
 define i64 @misaligned_ld(i64* %p) {
 ; CHECK-LABEL: misaligned_ld:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 4
-; CHECK-NEXT:    lwbrx 4, 3, 4
-; CHECK-NEXT:    lwbrx 3, 0, 3
-; CHECK-NEXT:    rldimi 3, 4, 32, 0
+; CHECK-NEXT:    ld 4, 0(3)
+; CHECK-NEXT:    rotldi 5, 4, 16
+; CHECK-NEXT:    rotldi 3, 4, 8
+; CHECK-NEXT:    rldimi 3, 5, 8, 48
+; CHECK-NEXT:    rotldi 5, 4, 24
+; CHECK-NEXT:    rldimi 3, 5, 16, 40
+; CHECK-NEXT:    rotldi 5, 4, 32
+; CHECK-NEXT:    rldimi 3, 5, 24, 32
+; CHECK-NEXT:    rotldi 5, 4, 48
+; CHECK-NEXT:    rldimi 3, 5, 40, 16
+; CHECK-NEXT:    rotldi 5, 4, 56
+; CHECK-NEXT:    rldimi 3, 5, 48, 8
+; CHECK-NEXT:    rldimi 3, 4, 56, 0
 ; CHECK-NEXT:    blr
   %x = load i64, i64* %p, align 1
   %b = call i64 @llvm.bswap.i64(i64 %x)