[PATCH] D104921: [RISCV] Lower more BUILD_VECTOR sequences to RVV's VID

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1569
+  if (auto SimpleVID = isSimpleVIDSequence(Op)) {
+    // Only emit VIDs with suitably-small steps/addends. We use imm6 is a
+    // threshold since it's the immediate value many RVV instructions accept.
----------------
Isn't it simm5?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1584
+        unsigned Opcode = ISD::MUL;
+        if (Step > 0 && isPowerOf2_64(Step)) {
+          Opcode = ISD::SHL;
----------------
Step == -1 -> negate?


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll:179
+; RV32-NEXT:    addi a0, zero, -1
+; RV32-NEXT:    vmadd.vx v28, a0, v25
 ; RV32-NEXT:    addi a0, zero, 12
----------------
This can I think be

```
vid.v v28
vrsub.vx v28, 4
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D104921/new/

https://reviews.llvm.org/D104921