[PATCH] D104903: [X86] Limit the scaled element type to i64/f64

[Pengfei Wang via Phabricator via llvm-commits]

pengfei created this revision.
pengfei added a reviewer: RKSimon.
Herald added a subscriber: hiraditya.
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Herald added a subscriber: llvm-commits.

This patch tries to fix PR50823.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104903

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/pr50823.ll


Index: llvm/test/CodeGen/X86/pr50823.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/pr50823.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s
+
+%v8_uniform_FVector3 = type { float, float, float }
+
+; Function Attrs: argmemonly nofree nounwind readonly
+declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x i32>) #0
+
+; Function Attrs: nofree nosync nounwind readnone
+declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) #1
+
+; Function Attrs: nounwind
+define void @test___REFs_5B_unFVector3_5D_un_3C_unf_3E_(%v8_uniform_FVector3* noalias nocapture %Out, float* noalias %In, <8 x i32> %__mask) local_unnamed_addr #2 {
+; CHECK-LABEL: test___REFs_5B_unFVector3_5D_un_3C_unf_3E_:
+; CHECK:       # %bb.0: # %allocas
+; CHECK-NEXT:    vmovups (%rsi), %xmm0
+; CHECK-NEXT:    vhaddps 32(%rsi), %xmm0, %xmm0
+; CHECK-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,1,0,1]
+; CHECK-NEXT:    vhaddps %ymm0, %ymm0, %ymm0
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmovss %xmm0, (%rdi)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+allocas:
+  %ptr_cast_for_load = bitcast float* %In to <8 x float>*
+  %ptr_masked_load74 = load <8 x float>, <8 x float>* %ptr_cast_for_load, align 4
+  %ptr8096 = getelementptr float, float* %In, i64 8
+  %ptr_cast_for_load81 = bitcast float* %ptr8096 to <8 x float>*
+  %ptr80_masked_load82 = load <8 x float>, <8 x float>* %ptr_cast_for_load81, align 4
+  %ret_7.i.i = shufflevector <8 x float> %ptr_masked_load74, <8 x float> %ptr80_masked_load82, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+  %Out_load19 = getelementptr %v8_uniform_FVector3, %v8_uniform_FVector3* %Out, i64 0, i32 0
+  %v1.i.i100 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %ret_7.i.i, <8 x float> %ret_7.i.i) #2
+  %v2.i.i101 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %v1.i.i100, <8 x float> %v1.i.i100) #2
+  %scalar1.i.i102 = extractelement <8 x float> %v2.i.i101, i32 0
+  %scalar2.i.i103 = extractelement <8 x float> %v2.i.i101, i32 4
+  %sum.i.i104 = fadd float %scalar1.i.i102, %scalar2.i.i103
+  store float %sum.i.i104, float* %Out_load19, align 4
+  ret void
+}
+
+attributes #0 = { argmemonly nofree nounwind readonly }
+attributes #1 = { nofree nosync nounwind readnone }
+attributes #2 = { nounwind }
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -43635,6 +43635,7 @@
   }
 
   // Attempt to fold HOP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y)).
+  int Size = VT.getVectorNumElements();
   if (VT.is256BitVector() && Subtarget.hasInt256()) {
     SmallVector<int> Mask0, Mask1;
     SmallVector<SDValue> Ops0, Ops1;
@@ -43646,8 +43647,8 @@
                [](SDValue Op) { return Op.getValueType().is256BitVector(); }) &&
         all_of(Ops1,
                [](SDValue Op) { return Op.getValueType().is256BitVector(); }) &&
-        scaleShuffleElements(Mask0, 2, ScaledMask0) &&
-        scaleShuffleElements(Mask1, 2, ScaledMask1)) {
+        scaleShuffleElements(Mask0, Size == 8 ? 4 : 2, ScaledMask0) &&
+        scaleShuffleElements(Mask1, Size == 8 ? 4 : 2, ScaledMask1)) {
       SDValue Op00 = peekThroughBitcasts(Ops0.front());
       SDValue Op10 = peekThroughBitcasts(Ops1.front());
       SDValue Op01 = peekThroughBitcasts(Ops0.back());
@@ -43659,7 +43660,13 @@
       if ((Op00 == Op10) && (Op01 == Op11)) {
         SmallVector<int, 4> ShuffleMask;
         ShuffleMask.append(ScaledMask0.begin(), ScaledMask0.end());
-        ShuffleMask.append(ScaledMask1.begin(), ScaledMask1.end());
+        if (Size == 8) {
+          for (int I = 0; I < 4; ++I)
+            if (ShuffleMask[I] != ScaledMask1[I])
+              return SDValue();
+        } else {
+          ShuffleMask.append(ScaledMask1.begin(), ScaledMask1.end());
+        }
         MVT ShufVT = VT.isFloatingPoint() ? MVT::v4f64 : MVT::v4i64;
         SDValue Res = DAG.getNode(Opcode, DL, VT, DAG.getBitcast(SrcVT, Op00),
                                   DAG.getBitcast(SrcVT, Op01));


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