[llvm] a08fc13 - [PowerPC] Change VSRpRC allocation order
Qiu Chaofan via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 25 01:05:35 PDT 2021
Author: Qiu Chaofan
Date: 2021-06-25T16:04:41+08:00
New Revision: a08fc1361aa307874045edde8c7af7642f4713a0
URL: https://github.com/llvm/llvm-project/commit/a08fc1361aa307874045edde8c7af7642f4713a0
DIFF: https://github.com/llvm/llvm-project/commit/a08fc1361aa307874045edde8c7af7642f4713a0.diff
LOG: [PowerPC] Change VSRpRC allocation order
On PowerPC, VSRpRC represents the pairs of even and odd VSX register,
and VRRC corresponds to higher 32 VSX registers. In some cases, extra
copies are produced when handling incoming VRRC arguments with VSRpRC.
This patch changes allocation order of VSRpRC to eliminate this kind of
copy.
Stack frame sizes may increase if allocating non-volatile registers, and
some other vector copies happen. They need fix in future changes.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D104855
Added:
Modified:
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
llvm/test/CodeGen/PowerPC/mma-outer-product.ll
llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
llvm/test/CodeGen/PowerPC/spill-vec-pair.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 6bc8f75f38641..6fbff72d1ac91 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -468,14 +468,20 @@ def UACCRC : RegisterClass<"PPC", [v512i1], 128,
let Size = 512;
}
-// Allocate in the same order as the underlying VSX registers.
+// FIXME: This allocation order may increase stack frame size when allocating
+// non-volatile registers.
+//
+// Placing Altivec registers first and allocate the rest as underlying VSX
+// ones, to reduce interference with accumulator registers (lower 32 VSRs).
+// This reduces copies when loading for accumulators, which is common use for
+// paired VSX registers.
def VSRpRC :
RegisterClass<"PPC", [v256i1], 128,
- (add (sequence "VSRp%u", 0, 6),
- (sequence "VSRp%u", 15, 7), VSRp17, VSRp18,
- VSRp16, VSRp19, VSRp20, VSRp21, VSRp22, VSRp23,
- VSRp24, VSRp25, VSRp31, VSRp30, VSRp29, VSRp28,
- VSRp27, VSRp26)> {
+ (add VSRp17, VSRp18, VSRp16, VSRp19, VSRp20, VSRp21,
+ VSRp22, VSRp23, VSRp24, VSRp25, VSRp31, VSRp30,
+ VSRp29, VSRp28, VSRp27, VSRp26,
+ (sequence "VSRp%u", 0, 6),
+ (sequence "VSRp%u", 15, 7))> {
let Size = 256;
}
diff --git a/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll b/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
index 7365ded9922a8..78f6ec0204bed 100644
--- a/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
+++ b/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
@@ -23,15 +23,15 @@ define void @foo(i32 zeroext %n, <256 x i1>* %ptr, <256 x i1>* %ptr2) {
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: #
-; CHECK-NEXT: lxvp vsp0, -64(r3)
-; CHECK-NEXT: lxvp vsp2, -32(r3)
-; CHECK-NEXT: lxvp vsp4, 0(r3)
-; CHECK-NEXT: lxvp vsp6, 32(r3)
+; CHECK-NEXT: lxvp vsp34, -64(r3)
+; CHECK-NEXT: lxvp vsp36, -32(r3)
+; CHECK-NEXT: lxvp vsp32, 0(r3)
+; CHECK-NEXT: lxvp vsp38, 32(r3)
; CHECK-NEXT: addi r3, r3, 1
-; CHECK-NEXT: stxvp vsp0, -64(r4)
-; CHECK-NEXT: stxvp vsp2, -32(r4)
-; CHECK-NEXT: stxvp vsp4, 0(r4)
-; CHECK-NEXT: stxvp vsp6, 32(r4)
+; CHECK-NEXT: stxvp vsp34, -64(r4)
+; CHECK-NEXT: stxvp vsp36, -32(r4)
+; CHECK-NEXT: stxvp vsp32, 0(r4)
+; CHECK-NEXT: stxvp vsp38, 32(r4)
; CHECK-NEXT: addi r4, r4, 1
; CHECK-NEXT: bdnz .LBB0_2
; CHECK-NEXT: # %bb.3: # %for.cond.cleanup
@@ -49,15 +49,15 @@ define void @foo(i32 zeroext %n, <256 x i1>* %ptr, <256 x i1>* %ptr2) {
; CHECK-BE-NEXT: .p2align 4
; CHECK-BE-NEXT: .LBB0_2: # %for.body
; CHECK-BE-NEXT: #
-; CHECK-BE-NEXT: lxvp vsp0, -64(r3)
-; CHECK-BE-NEXT: lxvp vsp2, -32(r3)
-; CHECK-BE-NEXT: lxvp vsp4, 0(r3)
-; CHECK-BE-NEXT: lxvp vsp6, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp34, -64(r3)
+; CHECK-BE-NEXT: lxvp vsp36, -32(r3)
+; CHECK-BE-NEXT: lxvp vsp32, 0(r3)
+; CHECK-BE-NEXT: lxvp vsp38, 32(r3)
; CHECK-BE-NEXT: addi r3, r3, 1
-; CHECK-BE-NEXT: stxvp vsp0, -64(r4)
-; CHECK-BE-NEXT: stxvp vsp2, -32(r4)
-; CHECK-BE-NEXT: stxvp vsp4, 0(r4)
-; CHECK-BE-NEXT: stxvp vsp6, 32(r4)
+; CHECK-BE-NEXT: stxvp vsp34, -64(r4)
+; CHECK-BE-NEXT: stxvp vsp36, -32(r4)
+; CHECK-BE-NEXT: stxvp vsp32, 0(r4)
+; CHECK-BE-NEXT: stxvp vsp38, 32(r4)
; CHECK-BE-NEXT: addi r4, r4, 1
; CHECK-BE-NEXT: bdnz .LBB0_2
; CHECK-BE-NEXT: # %bb.3: # %for.cond.cleanup
diff --git a/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll b/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
index 723df50f9f328..bdab51bf2d0c2 100644
--- a/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
@@ -27,13 +27,13 @@ define void @foo(i64* %.n, [0 x %_elem_type_of_x]* %.x, [0 x %_elem_type_of_y]*
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %_loop_1_do_
; CHECK-NEXT: #
-; CHECK-NEXT: lxvp vsp2, 0(r3)
-; CHECK-NEXT: lxvp vsp4, 32(r3)
+; CHECK-NEXT: lxvp vsp34, 0(r3)
+; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: addi r3, r3, 128
-; CHECK-NEXT: xvadddp vs0, vs0, vs3
-; CHECK-NEXT: xvadddp vs0, vs0, vs2
-; CHECK-NEXT: xvadddp vs0, vs0, vs5
-; CHECK-NEXT: xvadddp vs0, vs0, vs4
+; CHECK-NEXT: xvadddp vs0, vs0, vs35
+; CHECK-NEXT: xvadddp vs0, vs0, vs34
+; CHECK-NEXT: xvadddp vs0, vs0, vs37
+; CHECK-NEXT: xvadddp vs0, vs0, vs36
; CHECK-NEXT: bdnz .LBB0_2
; CHECK-NEXT: # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge
; CHECK-NEXT: stxv vs0, 0(r6)
@@ -54,13 +54,13 @@ define void @foo(i64* %.n, [0 x %_elem_type_of_x]* %.x, [0 x %_elem_type_of_y]*
; CHECK-BE-NEXT: .p2align 5
; CHECK-BE-NEXT: .LBB0_2: # %_loop_1_do_
; CHECK-BE-NEXT: #
-; CHECK-BE-NEXT: lxvp vsp2, 0(r3)
-; CHECK-BE-NEXT: lxvp vsp4, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp34, 0(r3)
+; CHECK-BE-NEXT: lxvp vsp36, 32(r3)
; CHECK-BE-NEXT: addi r3, r3, 128
-; CHECK-BE-NEXT: xvadddp vs0, vs0, vs2
-; CHECK-BE-NEXT: xvadddp vs0, vs0, vs3
-; CHECK-BE-NEXT: xvadddp vs0, vs0, vs4
-; CHECK-BE-NEXT: xvadddp vs0, vs0, vs5
+; CHECK-BE-NEXT: xvadddp vs0, vs0, vs34
+; CHECK-BE-NEXT: xvadddp vs0, vs0, vs35
+; CHECK-BE-NEXT: xvadddp vs0, vs0, vs36
+; CHECK-BE-NEXT: xvadddp vs0, vs0, vs37
; CHECK-BE-NEXT: bdnz .LBB0_2
; CHECK-BE-NEXT: # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge
; CHECK-BE-NEXT: stxv vs0, 0(r6)
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
index b152c1a9fc73d..90f38ee462896 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -134,20 +134,20 @@ entry:
define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; LE-PAIRED-LABEL: testLdStPair:
; LE-PAIRED: # %bb.0: # %entry
-; LE-PAIRED-NEXT: plxv vs1, g at PCREL+32(0), 1
-; LE-PAIRED-NEXT: plxv vs0, g at PCREL+48(0), 1
-; LE-PAIRED-NEXT: pstxv vs1, g at PCREL+64(0), 1
-; LE-PAIRED-NEXT: pstxv vs0, g at PCREL+80(0), 1
+; LE-PAIRED-NEXT: plxv v3, g at PCREL+32(0), 1
+; LE-PAIRED-NEXT: plxv v2, g at PCREL+48(0), 1
+; LE-PAIRED-NEXT: pstxv v3, g at PCREL+64(0), 1
+; LE-PAIRED-NEXT: pstxv v2, g at PCREL+80(0), 1
; LE-PAIRED-NEXT: blr
;
; BE-PAIRED-LABEL: testLdStPair:
; BE-PAIRED: # %bb.0: # %entry
; BE-PAIRED-NEXT: addis r3, r2, g at toc@ha
; BE-PAIRED-NEXT: addi r3, r3, g at toc@l
-; BE-PAIRED-NEXT: lxv vs1, 48(r3)
-; BE-PAIRED-NEXT: lxv vs0, 32(r3)
-; BE-PAIRED-NEXT: stxv vs1, 80(r3)
-; BE-PAIRED-NEXT: stxv vs0, 64(r3)
+; BE-PAIRED-NEXT: lxv v3, 48(r3)
+; BE-PAIRED-NEXT: lxv v2, 32(r3)
+; BE-PAIRED-NEXT: stxv v3, 80(r3)
+; BE-PAIRED-NEXT: stxv v2, 64(r3)
; BE-PAIRED-NEXT: blr
entry:
%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 1
@@ -163,12 +163,12 @@ define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; LE-PAIRED-NEXT: sldi r3, r3, 5
; LE-PAIRED-NEXT: paddi r5, 0, g at PCREL, 1
; LE-PAIRED-NEXT: add r6, r5, r3
-; LE-PAIRED-NEXT: lxvx vs1, r5, r3
+; LE-PAIRED-NEXT: lxvx v3, r5, r3
; LE-PAIRED-NEXT: sldi r3, r4, 5
-; LE-PAIRED-NEXT: lxv vs0, 16(r6)
+; LE-PAIRED-NEXT: lxv v2, 16(r6)
; LE-PAIRED-NEXT: add r4, r5, r3
-; LE-PAIRED-NEXT: stxvx vs1, r5, r3
-; LE-PAIRED-NEXT: stxv vs0, 16(r4)
+; LE-PAIRED-NEXT: stxvx v3, r5, r3
+; LE-PAIRED-NEXT: stxv v2, 16(r4)
; LE-PAIRED-NEXT: blr
;
; BE-PAIRED-LABEL: testXLdStPair:
@@ -177,12 +177,12 @@ define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; BE-PAIRED-NEXT: sldi r3, r3, 5
; BE-PAIRED-NEXT: addi r5, r5, g at toc@l
; BE-PAIRED-NEXT: add r6, r5, r3
-; BE-PAIRED-NEXT: lxvx vs0, r5, r3
+; BE-PAIRED-NEXT: lxvx v2, r5, r3
; BE-PAIRED-NEXT: sldi r3, r4, 5
-; BE-PAIRED-NEXT: lxv vs1, 16(r6)
+; BE-PAIRED-NEXT: lxv v3, 16(r6)
; BE-PAIRED-NEXT: add r4, r5, r3
-; BE-PAIRED-NEXT: stxvx vs0, r5, r3
-; BE-PAIRED-NEXT: stxv vs1, 16(r4)
+; BE-PAIRED-NEXT: stxvx v2, r5, r3
+; BE-PAIRED-NEXT: stxv v3, 16(r4)
; BE-PAIRED-NEXT: blr
entry:
%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %SrcIdx
@@ -195,10 +195,10 @@ entry:
define dso_local void @testUnalignedLdStPair() {
; LE-PAIRED-LABEL: testUnalignedLdStPair:
; LE-PAIRED: # %bb.0: # %entry
-; LE-PAIRED-NEXT: plxv vs1, g at PCREL+11(0), 1
-; LE-PAIRED-NEXT: plxv vs0, g at PCREL+27(0), 1
-; LE-PAIRED-NEXT: pstxv vs1, g at PCREL+19(0), 1
-; LE-PAIRED-NEXT: pstxv vs0, g at PCREL+35(0), 1
+; LE-PAIRED-NEXT: plxv v3, g at PCREL+11(0), 1
+; LE-PAIRED-NEXT: plxv v2, g at PCREL+27(0), 1
+; LE-PAIRED-NEXT: pstxv v3, g at PCREL+19(0), 1
+; LE-PAIRED-NEXT: pstxv v2, g at PCREL+35(0), 1
; LE-PAIRED-NEXT: blr
;
; BE-PAIRED-LABEL: testUnalignedLdStPair:
@@ -206,13 +206,13 @@ define dso_local void @testUnalignedLdStPair() {
; BE-PAIRED-NEXT: addis r3, r2, g at toc@ha
; BE-PAIRED-NEXT: li r4, 11
; BE-PAIRED-NEXT: addi r3, r3, g at toc@l
-; BE-PAIRED-NEXT: lxvx vs0, r3, r4
+; BE-PAIRED-NEXT: lxvx v2, r3, r4
; BE-PAIRED-NEXT: li r4, 27
-; BE-PAIRED-NEXT: lxvx vs1, r3, r4
+; BE-PAIRED-NEXT: lxvx v3, r3, r4
; BE-PAIRED-NEXT: li r4, 35
-; BE-PAIRED-NEXT: stxvx vs1, r3, r4
+; BE-PAIRED-NEXT: stxvx v3, r3, r4
; BE-PAIRED-NEXT: li r4, 19
-; BE-PAIRED-NEXT: stxvx vs0, r3, r4
+; BE-PAIRED-NEXT: stxvx v2, r3, r4
; BE-PAIRED-NEXT: blr
entry:
%0 = bitcast <256 x i1>* @g to i8*
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
index f5e7e8a43a024..c269061556f4c 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
@@ -38,10 +38,10 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: bl foo at notoc
; CHECK-NEXT: lxvp vsp0, 64(r1)
; CHECK-NEXT: lxvp vsp2, 32(r1)
-; CHECK-NEXT: lxvp vsp4, 128(r1) # 32-byte Folded Reload
-; CHECK-NEXT: lxvp vsp6, 96(r1) # 32-byte Folded Reload
+; CHECK-NEXT: lxvp vsp34, 128(r1) # 32-byte Folded Reload
+; CHECK-NEXT: lxvp vsp36, 96(r1) # 32-byte Folded Reload
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: xvf16ger2pp acc0, vs4, vs6
+; CHECK-NEXT: xvf16ger2pp acc0, v2, v4
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r30)
; CHECK-NEXT: stxv vs1, 32(r30)
@@ -82,10 +82,10 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: lxvp vsp0, 112(r1)
; CHECK-BE-NEXT: lxvp vsp2, 144(r1)
-; CHECK-BE-NEXT: lxvp vsp4, 208(r1) # 32-byte Folded Reload
-; CHECK-BE-NEXT: lxvp vsp6, 176(r1) # 32-byte Folded Reload
+; CHECK-BE-NEXT: lxvp vsp34, 208(r1) # 32-byte Folded Reload
+; CHECK-BE-NEXT: lxvp vsp36, 176(r1) # 32-byte Folded Reload
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: xvf16ger2pp acc0, vs4, vs6
+; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v4
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r30)
; CHECK-BE-NEXT: stxvx vs0, 0, r30
diff --git a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
index 1a8d2ece5e644..ca0e2fdf8265f 100644
--- a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -11,16 +11,11 @@ declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <
define void @ass_acc(<512 x i1>* %ptr, <16 x i8> %vc) {
; CHECK-LABEL: ass_acc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor vs1, v2, v2
-; CHECK-NEXT: xxlor vs0, vs1, vs1
-; CHECK-NEXT: xxlor vs4, vs0, vs0
-; CHECK-NEXT: xxlor vs5, vs1, vs1
-; CHECK-NEXT: xxlor vs6, vs0, vs0
-; CHECK-NEXT: xxlor vs7, vs1, vs1
-; CHECK-NEXT: xxlor vs0, vs4, vs4
-; CHECK-NEXT: xxlor vs1, vs5, vs5
-; CHECK-NEXT: xxlor vs2, vs6, vs6
-; CHECK-NEXT: xxlor vs3, vs7, vs7
+; CHECK-NEXT: vmr v3, v2
+; CHECK-NEXT: xxlor vs0, v2, v2
+; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: xxlor vs2, v2, v2
+; CHECK-NEXT: xxlor vs3, v3, v3
; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3)
@@ -29,16 +24,11 @@ define void @ass_acc(<512 x i1>* %ptr, <16 x i8> %vc) {
;
; CHECK-BE-LABEL: ass_acc:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxlor vs1, v2, v2
-; CHECK-BE-NEXT: xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT: xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs6, vs0, vs0
-; CHECK-BE-NEXT: xxlor vs7, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT: xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT: xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT: xxlor vs3, vs7, vs7
+; CHECK-BE-NEXT: vmr v3, v2
+; CHECK-BE-NEXT: xxlor vs0, v2, v2
+; CHECK-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-BE-NEXT: xxlor vs2, v2, v2
+; CHECK-BE-NEXT: xxlor vs3, v3, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3)
@@ -55,16 +45,11 @@ declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
define void @int_xxmtacc(<512 x i1>* %ptr, <16 x i8> %vc) {
; CHECK-LABEL: int_xxmtacc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor vs1, v2, v2
-; CHECK-NEXT: xxlor vs0, vs1, vs1
-; CHECK-NEXT: xxlor vs4, vs0, vs0
-; CHECK-NEXT: xxlor vs5, vs1, vs1
-; CHECK-NEXT: xxlor vs6, vs0, vs0
-; CHECK-NEXT: xxlor vs7, vs1, vs1
-; CHECK-NEXT: xxlor vs0, vs4, vs4
-; CHECK-NEXT: xxlor vs1, vs5, vs5
-; CHECK-NEXT: xxlor vs2, vs6, vs6
-; CHECK-NEXT: xxlor vs3, vs7, vs7
+; CHECK-NEXT: vmr v3, v2
+; CHECK-NEXT: xxlor vs0, v2, v2
+; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: xxlor vs2, v2, v2
+; CHECK-NEXT: xxlor vs3, v3, v3
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3)
@@ -74,16 +59,11 @@ define void @int_xxmtacc(<512 x i1>* %ptr, <16 x i8> %vc) {
;
; CHECK-BE-LABEL: int_xxmtacc:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxlor vs1, v2, v2
-; CHECK-BE-NEXT: xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT: xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs6, vs0, vs0
-; CHECK-BE-NEXT: xxlor vs7, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT: xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT: xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT: xxlor vs3, vs7, vs7
+; CHECK-BE-NEXT: vmr v3, v2
+; CHECK-BE-NEXT: xxlor vs0, v2, v2
+; CHECK-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-BE-NEXT: xxlor vs2, v2, v2
+; CHECK-BE-NEXT: xxlor vs3, v3, v3
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
@@ -104,16 +84,11 @@ declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
define void @int_xxmfacc(<512 x i1>* %ptr, <16 x i8> %vc) {
; CHECK-LABEL: int_xxmfacc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor vs1, v2, v2
-; CHECK-NEXT: xxlor vs0, vs1, vs1
-; CHECK-NEXT: xxlor vs4, vs0, vs0
-; CHECK-NEXT: xxlor vs5, vs1, vs1
-; CHECK-NEXT: xxlor vs6, vs0, vs0
-; CHECK-NEXT: xxlor vs7, vs1, vs1
-; CHECK-NEXT: xxlor vs0, vs4, vs4
-; CHECK-NEXT: xxlor vs1, vs5, vs5
-; CHECK-NEXT: xxlor vs2, vs6, vs6
-; CHECK-NEXT: xxlor vs3, vs7, vs7
+; CHECK-NEXT: vmr v3, v2
+; CHECK-NEXT: xxlor vs0, v2, v2
+; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: xxlor vs2, v2, v2
+; CHECK-NEXT: xxlor vs3, v3, v3
; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3)
@@ -122,16 +97,11 @@ define void @int_xxmfacc(<512 x i1>* %ptr, <16 x i8> %vc) {
;
; CHECK-BE-LABEL: int_xxmfacc:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxlor vs1, v2, v2
-; CHECK-BE-NEXT: xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT: xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs6, vs0, vs0
-; CHECK-BE-NEXT: xxlor vs7, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT: xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT: xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT: xxlor vs3, vs7, vs7
+; CHECK-BE-NEXT: vmr v3, v2
+; CHECK-BE-NEXT: xxlor vs0, v2, v2
+; CHECK-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-BE-NEXT: xxlor vs2, v2, v2
+; CHECK-BE-NEXT: xxlor vs3, v3, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3)
@@ -657,9 +627,9 @@ define void @test_ldst_1(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: li r3, 8
-; CHECK-NEXT: lxvpx vsp4, r4, r3
+; CHECK-NEXT: lxvpx vsp36, r4, r3
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -674,9 +644,9 @@ define void @test_ldst_1(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: li r3, 8
-; CHECK-BE-NEXT: lxvpx vsp4, r4, r3
+; CHECK-BE-NEXT: lxvpx vsp36, r4, r3
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -703,9 +673,9 @@ define void @test_ldst_2(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
-; CHECK-NEXT: lxvp vsp4, 0(r4)
+; CHECK-NEXT: lxvp vsp36, 0(r4)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: xvf64gernp acc0, vsp4, v2
+; CHECK-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -719,9 +689,9 @@ define void @test_ldst_2(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp4, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp36, 0(r4)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: xvf64gernp acc0, vsp4, v2
+; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -747,9 +717,9 @@ define void @test_ldst_3(i8* nocapture readonly %vqp, i64 %offs, <256 x i1>* %vp
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
-; CHECK-NEXT: lxvp vsp4, 0(r5)
+; CHECK-NEXT: lxvp vsp36, 0(r5)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: xvf64gernp acc0, vsp4, v2
+; CHECK-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r9)
; CHECK-NEXT: stxv vs1, 32(r9)
@@ -763,9 +733,9 @@ define void @test_ldst_3(i8* nocapture readonly %vqp, i64 %offs, <256 x i1>* %vp
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp4, 0(r5)
+; CHECK-BE-NEXT: lxvp vsp36, 0(r5)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: xvf64gernp acc0, vsp4, v2
+; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r9)
; CHECK-BE-NEXT: stxv vs0, 0(r9)
diff --git a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
index 856cb9d384c1a..9c27323fafdcf 100644
--- a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
@@ -12,51 +12,51 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-LABEL: intrinsics1:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
-; CHECK-NEXT: xxlor vs1, v4, v4
+; CHECK-NEXT: vmr v1, v4
; CHECK-NEXT: vmr v4, v3
; CHECK-NEXT: ld r3, 96(r1)
-; CHECK-NEXT: xxlor vs0, v2, v2
-; CHECK-NEXT: xxlor vs3, v2, v2
-; CHECK-NEXT: xxlor vs2, v5, v5
-; CHECK-NEXT: xxlor vs4, vs0, vs0
-; CHECK-NEXT: xxlor vs5, vs1, vs1
-; CHECK-NEXT: xxlor vs6, v4, v4
-; CHECK-NEXT: xxlor vs7, v5, v5
-; CHECK-NEXT: xxmtacc acc1
-; CHECK-NEXT: xvi4ger8pp acc1, v2, v3
-; CHECK-NEXT: xvf16ger2pp acc1, v2, vs1
-; CHECK-NEXT: pmxvf32gerpn acc1, v3, v5, 0, 0
-; CHECK-NEXT: pmxvf64gernp acc1, vsp2, vs0, 0, 0
-; CHECK-NEXT: xxmfacc acc1
-; CHECK-NEXT: stxv vs4, 48(r3)
-; CHECK-NEXT: stxv vs5, 32(r3)
-; CHECK-NEXT: stxv vs6, 16(r3)
-; CHECK-NEXT: stxvx vs7, 0, r3
+; CHECK-NEXT: vmr v0, v2
+; CHECK-NEXT: xxlor vs0, v0, v0
+; CHECK-NEXT: xxlor vs1, v1, v1
+; CHECK-NEXT: xxlor vs2, v4, v4
+; CHECK-NEXT: xxlor vs3, v5, v5
+; CHECK-NEXT: xxmtacc acc0
+; CHECK-NEXT: xvi4ger8pp acc0, v2, v3
+; CHECK-NEXT: xvf16ger2pp acc0, v2, v1
+; CHECK-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0
+; CHECK-NEXT: vmr v3, v0
+; CHECK-NEXT: vmr v2, v5
+; CHECK-NEXT: pmxvf64gernp acc0, vsp34, v0, 0, 0
+; CHECK-NEXT: xxmfacc acc0
+; CHECK-NEXT: stxv vs0, 48(r3)
+; CHECK-NEXT: stxv vs1, 32(r3)
+; CHECK-NEXT: stxv vs2, 16(r3)
+; CHECK-NEXT: stxvx vs3, 0, r3
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: intrinsics1:
; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
-; CHECK-BE-NEXT: xxlor vs1, v4, v4
+; CHECK-BE-NEXT: vmr v1, v4
; CHECK-BE-NEXT: vmr v4, v3
; CHECK-BE-NEXT: ld r3, 112(r1)
-; CHECK-BE-NEXT: xxlor vs0, v2, v2
-; CHECK-BE-NEXT: xxlor vs3, v2, v2
-; CHECK-BE-NEXT: xxlor vs2, v5, v5
-; CHECK-BE-NEXT: xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT: xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT: xxlor vs6, v4, v4
-; CHECK-BE-NEXT: xxlor vs7, v5, v5
-; CHECK-BE-NEXT: xxmtacc acc1
-; CHECK-BE-NEXT: xvi4ger8pp acc1, v2, v3
-; CHECK-BE-NEXT: xvf16ger2pp acc1, v2, vs1
-; CHECK-BE-NEXT: pmxvf32gerpn acc1, v3, v5, 0, 0
-; CHECK-BE-NEXT: pmxvf64gernp acc1, vsp2, vs0, 0, 0
-; CHECK-BE-NEXT: xxmfacc acc1
-; CHECK-BE-NEXT: stxv vs5, 16(r3)
-; CHECK-BE-NEXT: stxvx vs4, 0, r3
-; CHECK-BE-NEXT: stxv vs7, 48(r3)
-; CHECK-BE-NEXT: stxv vs6, 32(r3)
+; CHECK-BE-NEXT: vmr v0, v2
+; CHECK-BE-NEXT: xxlor vs0, v0, v0
+; CHECK-BE-NEXT: xxlor vs1, v1, v1
+; CHECK-BE-NEXT: xxlor vs2, v4, v4
+; CHECK-BE-NEXT: xxlor vs3, v5, v5
+; CHECK-BE-NEXT: xxmtacc acc0
+; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v3
+; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v1
+; CHECK-BE-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0
+; CHECK-BE-NEXT: vmr v3, v0
+; CHECK-BE-NEXT: vmr v2, v5
+; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp34, v0, 0, 0
+; CHECK-BE-NEXT: xxmfacc acc0
+; CHECK-BE-NEXT: stxv vs1, 16(r3)
+; CHECK-BE-NEXT: stxvx vs0, 0, r3
+; CHECK-BE-NEXT: stxv vs3, 48(r3)
+; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
@@ -73,21 +73,21 @@ declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble
define void @intrinsics2(<16 x i8>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3, <16 x i8>* %ptr4, i8* %ptr) {
; CHECK-LABEL: intrinsics2:
; CHECK: # %bb.0:
-; CHECK-NEXT: lxv vs4, 0(r3)
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs6, 0(r5)
-; CHECK-NEXT: lxv vs7, 0(r6)
-; CHECK-NEXT: xxlor vs0, vs4, vs4
-; CHECK-NEXT: xxlor vs9, vs4, vs4
-; CHECK-NEXT: xxlor vs1, vs5, vs5
-; CHECK-NEXT: xxlor vs2, vs6, vs6
-; CHECK-NEXT: xxlor vs3, vs7, vs7
-; CHECK-NEXT: xxlor vs8, vs7, vs7
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: lxv v4, 0(r5)
+; CHECK-NEXT: lxv v5, 0(r6)
+; CHECK-NEXT: xxlor vs0, v2, v2
+; CHECK-NEXT: vmr v1, v2
+; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: xxlor vs2, v4, v4
+; CHECK-NEXT: xxlor vs3, v5, v5
+; CHECK-NEXT: vmr v0, v5
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: xvi8ger4pp acc0, vs4, vs5
-; CHECK-NEXT: xvf16ger2pn acc0, vs4, vs6
-; CHECK-NEXT: pmxvf32gernn acc0, vs5, vs7, 0, 0
-; CHECK-NEXT: pmxvf64gernn acc0, vsp8, vs4, 0, 0
+; CHECK-NEXT: xvi8ger4pp acc0, v2, v3
+; CHECK-NEXT: xvf16ger2pn acc0, v2, v4
+; CHECK-NEXT: pmxvf32gernn acc0, v3, v5, 0, 0
+; CHECK-NEXT: pmxvf64gernn acc0, vsp32, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs3, 0(r3)
; CHECK-NEXT: stxv vs2, 0(r4)
@@ -97,21 +97,21 @@ define void @intrinsics2(<16 x i8>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3, <
;
; CHECK-BE-LABEL: intrinsics2:
; CHECK-BE: # %bb.0:
-; CHECK-BE-NEXT: lxv vs4, 0(r3)
-; CHECK-BE-NEXT: lxv vs5, 0(r4)
-; CHECK-BE-NEXT: lxv vs6, 0(r5)
-; CHECK-BE-NEXT: lxv vs7, 0(r6)
-; CHECK-BE-NEXT: xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT: xxlor vs9, vs4, vs4
-; CHECK-BE-NEXT: xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT: xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT: xxlor vs3, vs7, vs7
-; CHECK-BE-NEXT: xxlor vs8, vs7, vs7
+; CHECK-BE-NEXT: lxv v2, 0(r3)
+; CHECK-BE-NEXT: lxv v3, 0(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r5)
+; CHECK-BE-NEXT: lxv v5, 0(r6)
+; CHECK-BE-NEXT: xxlor vs0, v2, v2
+; CHECK-BE-NEXT: vmr v1, v2
+; CHECK-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-BE-NEXT: xxlor vs2, v4, v4
+; CHECK-BE-NEXT: xxlor vs3, v5, v5
+; CHECK-BE-NEXT: vmr v0, v5
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: xvi8ger4pp acc0, vs4, vs5
-; CHECK-BE-NEXT: xvf16ger2pn acc0, vs4, vs6
-; CHECK-BE-NEXT: pmxvf32gernn acc0, vs5, vs7, 0, 0
-; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp8, vs4, 0, 0
+; CHECK-BE-NEXT: xvi8ger4pp acc0, v2, v3
+; CHECK-BE-NEXT: xvf16ger2pn acc0, v2, v4
+; CHECK-BE-NEXT: pmxvf32gernn acc0, v3, v5, 0, 0
+; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp32, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 0(r4)
@@ -1368,26 +1368,26 @@ declare <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>,
define void @test33(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test33:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv vs1, 0(r4)
-; CHECK-NEXT: lxv vs0, 16(r4)
-; CHECK-NEXT: xvf64ger acc1, vsp0, v2
-; CHECK-NEXT: xxmfacc acc1
-; CHECK-NEXT: stxv vs4, 48(r7)
-; CHECK-NEXT: stxv vs5, 32(r7)
-; CHECK-NEXT: stxv vs6, 16(r7)
-; CHECK-NEXT: stxv vs7, 0(r7)
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: xvf64ger acc0, vsp36, v2
+; CHECK-NEXT: xxmfacc acc0
+; CHECK-NEXT: stxv vs0, 48(r7)
+; CHECK-NEXT: stxv vs1, 32(r7)
+; CHECK-NEXT: stxv vs2, 16(r7)
+; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test33:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxv vs1, 16(r4)
-; CHECK-BE-NEXT: lxv vs0, 0(r4)
-; CHECK-BE-NEXT: xvf64ger acc1, vsp0, v2
-; CHECK-BE-NEXT: xxmfacc acc1
-; CHECK-BE-NEXT: stxv vs5, 16(r7)
-; CHECK-BE-NEXT: stxv vs4, 0(r7)
-; CHECK-BE-NEXT: stxv vs7, 48(r7)
-; CHECK-BE-NEXT: stxv vs6, 32(r7)
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: xvf64ger acc0, vsp36, v2
+; CHECK-BE-NEXT: xxmfacc acc0
+; CHECK-BE-NEXT: stxv vs1, 16(r7)
+; CHECK-BE-NEXT: stxv vs0, 0(r7)
+; CHECK-BE-NEXT: stxv vs3, 48(r7)
+; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vpp to <256 x i1>*
@@ -1409,9 +1409,9 @@ define void @test34(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: xvf64gerpp acc0, vsp4, v2
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: xvf64gerpp acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1426,9 +1426,9 @@ define void @test34(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: xvf64gerpp acc0, vsp4, v2
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: xvf64gerpp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -1457,9 +1457,9 @@ define void @test35(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: xvf64gerpn acc0, vsp4, v2
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: xvf64gerpn acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1474,9 +1474,9 @@ define void @test35(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: xvf64gerpn acc0, vsp4, v2
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: xvf64gerpn acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -1505,9 +1505,9 @@ define void @test36(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: xvf64gernp acc0, vsp4, v2
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1522,9 +1522,9 @@ define void @test36(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: xvf64gernp acc0, vsp4, v2
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -1553,9 +1553,9 @@ define void @test37(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: xvf64gernn acc0, vsp4, v2
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: xvf64gernn acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1570,9 +1570,9 @@ define void @test37(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: xvf64gernn acc0, vsp4, v2
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: xvf64gernn acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -1596,26 +1596,26 @@ declare <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test38(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test38:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv vs1, 0(r4)
-; CHECK-NEXT: lxv vs0, 16(r4)
-; CHECK-NEXT: pmxvf64ger acc1, vsp0, v2, 0, 0
-; CHECK-NEXT: xxmfacc acc1
-; CHECK-NEXT: stxv vs4, 48(r7)
-; CHECK-NEXT: stxv vs5, 32(r7)
-; CHECK-NEXT: stxv vs6, 16(r7)
-; CHECK-NEXT: stxv vs7, 0(r7)
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0
+; CHECK-NEXT: xxmfacc acc0
+; CHECK-NEXT: stxv vs0, 48(r7)
+; CHECK-NEXT: stxv vs1, 32(r7)
+; CHECK-NEXT: stxv vs2, 16(r7)
+; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test38:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxv vs1, 16(r4)
-; CHECK-BE-NEXT: lxv vs0, 0(r4)
-; CHECK-BE-NEXT: pmxvf64ger acc1, vsp0, v2, 0, 0
-; CHECK-BE-NEXT: xxmfacc acc1
-; CHECK-BE-NEXT: stxv vs5, 16(r7)
-; CHECK-BE-NEXT: stxv vs4, 0(r7)
-; CHECK-BE-NEXT: stxv vs7, 48(r7)
-; CHECK-BE-NEXT: stxv vs6, 32(r7)
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0
+; CHECK-BE-NEXT: xxmfacc acc0
+; CHECK-BE-NEXT: stxv vs1, 16(r7)
+; CHECK-BE-NEXT: stxv vs0, 0(r7)
+; CHECK-BE-NEXT: stxv vs3, 48(r7)
+; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vpp to <256 x i1>*
@@ -1637,9 +1637,9 @@ define void @test39(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: pmxvf64gerpp acc0, vsp4, v2, 0, 0
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: pmxvf64gerpp acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1654,9 +1654,9 @@ define void @test39(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: pmxvf64gerpp acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: pmxvf64gerpp acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -1685,9 +1685,9 @@ define void @test40(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: pmxvf64gerpn acc0, vsp4, v2, 0, 0
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: pmxvf64gerpn acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1702,9 +1702,9 @@ define void @test40(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: pmxvf64gerpn acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: pmxvf64gerpn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -1733,9 +1733,9 @@ define void @test41(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: pmxvf64gernp acc0, vsp4, v2, 0, 0
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: pmxvf64gernp acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1750,9 +1750,9 @@ define void @test41(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
@@ -1781,9 +1781,9 @@ define void @test42(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: lxv vs5, 0(r4)
-; CHECK-NEXT: lxv vs4, 16(r4)
-; CHECK-NEXT: pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-NEXT: lxv v5, 0(r4)
+; CHECK-NEXT: lxv v4, 16(r4)
+; CHECK-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
@@ -1798,9 +1798,9 @@ define void @test42(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT: lxv v5, 16(r4)
+; CHECK-BE-NEXT: lxv v4, 0(r4)
+; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
diff --git a/llvm/test/CodeGen/PowerPC/mma-phi-accs.ll b/llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
index d5a3cc963f5f5..f5b05f40e6b30 100644
--- a/llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
@@ -18,17 +18,17 @@ define void @testPHI1(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) {
; CHECK-NEXT: blt cr0, .LBB0_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: clrldi r5, r5, 32
-; CHECK-NEXT: lxv vs4, 0(r4)
-; CHECK-NEXT: lxv vs5, 16(r4)
+; CHECK-NEXT: lxv v2, 0(r4)
+; CHECK-NEXT: lxv v3, 16(r4)
; CHECK-NEXT: addi r4, r4, 32
; CHECK-NEXT: addi r5, r5, -2
; CHECK-NEXT: mtctr r5
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: #
-; CHECK-NEXT: lxv vs6, 0(r4)
+; CHECK-NEXT: lxv vs4, 0(r4)
; CHECK-NEXT: addi r4, r4, 16
-; CHECK-NEXT: xvf64gerpp acc0, vsp4, vs6
+; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs4
; CHECK-NEXT: bdnz .LBB0_2
; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
; CHECK-NEXT: xxmfacc acc0
@@ -45,17 +45,17 @@ define void @testPHI1(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) {
; CHECK-BE-NEXT: blt cr0, .LBB0_3
; CHECK-BE-NEXT: # %bb.1: # %for.body.preheader
; CHECK-BE-NEXT: clrldi r5, r5, 32
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxv v3, 16(r4)
; CHECK-BE-NEXT: addi r4, r4, 32
; CHECK-BE-NEXT: addi r5, r5, -2
; CHECK-BE-NEXT: mtctr r5
; CHECK-BE-NEXT: .p2align 4
; CHECK-BE-NEXT: .LBB0_2: # %for.body
; CHECK-BE-NEXT: #
-; CHECK-BE-NEXT: lxv vs6, 0(r4)
+; CHECK-BE-NEXT: lxv vs4, 0(r4)
; CHECK-BE-NEXT: addi r4, r4, 16
-; CHECK-BE-NEXT: xvf64gerpp acc0, vsp4, vs6
+; CHECK-BE-NEXT: xvf64gerpp acc0, vsp34, vs4
; CHECK-BE-NEXT: bdnz .LBB0_2
; CHECK-BE-NEXT: .LBB0_3: # %for.cond.cleanup
; CHECK-BE-NEXT: xxmfacc acc0
@@ -108,11 +108,11 @@ declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)
define dso_local void @testPHI2(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) {
; CHECK-LABEL: testPHI2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv vs4, 0(r4)
-; CHECK-NEXT: lxv vs5, 16(r4)
-; CHECK-NEXT: lxv vs6, 32(r4)
+; CHECK-NEXT: lxv v2, 0(r4)
+; CHECK-NEXT: lxv v3, 16(r4)
+; CHECK-NEXT: lxv vs4, 32(r4)
; CHECK-NEXT: cmpwi r5, 4
-; CHECK-NEXT: xvf64ger acc0, vsp4, vs6
+; CHECK-NEXT: xvf64ger acc0, vsp34, vs4
; CHECK-NEXT: blt cr0, .LBB1_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: clrldi r5, r5, 32
@@ -122,9 +122,9 @@ define dso_local void @testPHI2(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %L
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB1_2: # %for.body
; CHECK-NEXT: #
-; CHECK-NEXT: lxv vs6, 0(r4)
+; CHECK-NEXT: lxv vs4, 0(r4)
; CHECK-NEXT: addi r4, r4, 16
-; CHECK-NEXT: xvf64gerpp acc0, vsp4, vs6
+; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs4
; CHECK-NEXT: bdnz .LBB1_2
; CHECK-NEXT: .LBB1_3: # %for.cond.cleanup
; CHECK-NEXT: xxmfacc acc0
@@ -136,11 +136,11 @@ define dso_local void @testPHI2(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %L
;
; CHECK-BE-LABEL: testPHI2:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxv vs4, 0(r4)
-; CHECK-BE-NEXT: lxv vs5, 16(r4)
-; CHECK-BE-NEXT: lxv vs6, 32(r4)
+; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxv v3, 16(r4)
+; CHECK-BE-NEXT: lxv vs4, 32(r4)
; CHECK-BE-NEXT: cmpwi r5, 4
-; CHECK-BE-NEXT: xvf64ger acc0, vsp4, vs6
+; CHECK-BE-NEXT: xvf64ger acc0, vsp34, vs4
; CHECK-BE-NEXT: blt cr0, .LBB1_3
; CHECK-BE-NEXT: # %bb.1: # %for.body.preheader
; CHECK-BE-NEXT: clrldi r5, r5, 32
@@ -150,9 +150,9 @@ define dso_local void @testPHI2(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %L
; CHECK-BE-NEXT: .p2align 4
; CHECK-BE-NEXT: .LBB1_2: # %for.body
; CHECK-BE-NEXT: #
-; CHECK-BE-NEXT: lxv vs6, 0(r4)
+; CHECK-BE-NEXT: lxv vs4, 0(r4)
; CHECK-BE-NEXT: addi r4, r4, 16
-; CHECK-BE-NEXT: xvf64gerpp acc0, vsp4, vs6
+; CHECK-BE-NEXT: xvf64gerpp acc0, vsp34, vs4
; CHECK-BE-NEXT: bdnz .LBB1_2
; CHECK-BE-NEXT: .LBB1_3: # %for.cond.cleanup
; CHECK-BE-NEXT: xxmfacc acc0
@@ -213,7 +213,7 @@ define void @testImplicitDef(<16 x i8>* %ptr) {
; CHECK-NEXT: # implicit-def: $acc0
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_2
; CHECK-NEXT: # %bb.1: # %label2
-; CHECK-NEXT: xvf64gerpp acc0, vsp0, vs0
+; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
; CHECK-NEXT: .LBB2_2: # %label3
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 0(r3)
@@ -224,7 +224,7 @@ define void @testImplicitDef(<16 x i8>* %ptr) {
; CHECK-BE-NEXT: # implicit-def: $acc0
; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB2_2
; CHECK-BE-NEXT: # %bb.1: # %label2
-; CHECK-BE-NEXT: xvf64gerpp acc0, vsp0, vs0
+; CHECK-BE-NEXT: xvf64gerpp acc0, vsp34, vs0
; CHECK-BE-NEXT: .LBB2_2: # %label3
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs3, 0(r3)
diff --git a/llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll b/llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
index 039f33a3b1177..258355d7e7b43 100644
--- a/llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
+++ b/llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
@@ -10,74 +10,74 @@ target triple = "powerpc64le-unknown-linux-gnu"
define void @foo(i32* %.m, i32* %.n, [0 x %_elem_type_of_a]* %.a, [0 x %_elem_type_of_x]* %.x, i32* %.l, <2 x double>* %.vy01, <2 x double>* %.vy02, <2 x double>* %.vy03, <2 x double>* %.vy04, <2 x double>* %.vy05, <2 x double>* %.vy06, <2 x double>* %.vy07, <2 x double>* %.vy08, <2 x double>* %.vy09, <2 x double>* %.vy0a, <2 x double>* %.vy0b, <2 x double>* %.vy0c, <2 x double>* %.vy21, <2 x double>* %.vy22, <2 x double>* %.vy23, <2 x double>* %.vy24, <2 x double>* %.vy25, <2 x double>* %.vy26, <2 x double>* %.vy27, <2 x double>* %.vy28, <2 x double>* %.vy29, <2 x double>* %.vy2a, <2 x double>* %.vy2b, <2 x double>* %.vy2c) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: stdu 1, -480(1)
-; CHECK-NEXT: .cfi_def_cfa_offset 480
-; CHECK-NEXT: .cfi_offset r14, -256
-; CHECK-NEXT: .cfi_offset r15, -248
-; CHECK-NEXT: .cfi_offset r16, -240
-; CHECK-NEXT: .cfi_offset r17, -232
-; CHECK-NEXT: .cfi_offset r18, -224
-; CHECK-NEXT: .cfi_offset r19, -216
-; CHECK-NEXT: .cfi_offset r20, -208
-; CHECK-NEXT: .cfi_offset r21, -200
-; CHECK-NEXT: .cfi_offset r22, -192
-; CHECK-NEXT: .cfi_offset r23, -184
-; CHECK-NEXT: .cfi_offset r24, -176
-; CHECK-NEXT: .cfi_offset r25, -168
-; CHECK-NEXT: .cfi_offset r26, -160
-; CHECK-NEXT: .cfi_offset r27, -152
-; CHECK-NEXT: .cfi_offset r28, -144
-; CHECK-NEXT: .cfi_offset r29, -136
-; CHECK-NEXT: .cfi_offset r30, -128
-; CHECK-NEXT: .cfi_offset r31, -120
-; CHECK-NEXT: .cfi_offset f18, -112
-; CHECK-NEXT: .cfi_offset f19, -104
-; CHECK-NEXT: .cfi_offset f20, -96
-; CHECK-NEXT: .cfi_offset f21, -88
-; CHECK-NEXT: .cfi_offset f22, -80
-; CHECK-NEXT: .cfi_offset f23, -72
-; CHECK-NEXT: .cfi_offset f24, -64
-; CHECK-NEXT: .cfi_offset f25, -56
-; CHECK-NEXT: .cfi_offset f26, -48
-; CHECK-NEXT: .cfi_offset f27, -40
-; CHECK-NEXT: .cfi_offset f28, -32
-; CHECK-NEXT: .cfi_offset f29, -24
+; CHECK-NEXT: stdu 1, -576(1)
+; CHECK-NEXT: .cfi_def_cfa_offset 576
+; CHECK-NEXT: .cfi_offset r14, -160
+; CHECK-NEXT: .cfi_offset r15, -152
+; CHECK-NEXT: .cfi_offset r16, -144
+; CHECK-NEXT: .cfi_offset r17, -136
+; CHECK-NEXT: .cfi_offset r18, -128
+; CHECK-NEXT: .cfi_offset r19, -120
+; CHECK-NEXT: .cfi_offset r20, -112
+; CHECK-NEXT: .cfi_offset r21, -104
+; CHECK-NEXT: .cfi_offset r22, -96
+; CHECK-NEXT: .cfi_offset r23, -88
+; CHECK-NEXT: .cfi_offset r24, -80
+; CHECK-NEXT: .cfi_offset r25, -72
+; CHECK-NEXT: .cfi_offset r26, -64
+; CHECK-NEXT: .cfi_offset r27, -56
+; CHECK-NEXT: .cfi_offset r28, -48
+; CHECK-NEXT: .cfi_offset r29, -40
+; CHECK-NEXT: .cfi_offset r30, -32
+; CHECK-NEXT: .cfi_offset r31, -24
; CHECK-NEXT: .cfi_offset f30, -16
; CHECK-NEXT: .cfi_offset f31, -8
+; CHECK-NEXT: .cfi_offset v20, -352
+; CHECK-NEXT: .cfi_offset v21, -336
+; CHECK-NEXT: .cfi_offset v22, -320
+; CHECK-NEXT: .cfi_offset v23, -304
+; CHECK-NEXT: .cfi_offset v24, -288
+; CHECK-NEXT: .cfi_offset v25, -272
+; CHECK-NEXT: .cfi_offset v26, -256
+; CHECK-NEXT: .cfi_offset v27, -240
+; CHECK-NEXT: .cfi_offset v28, -224
+; CHECK-NEXT: .cfi_offset v29, -208
+; CHECK-NEXT: .cfi_offset v30, -192
+; CHECK-NEXT: .cfi_offset v31, -176
; CHECK-NEXT: lwz 4, 0(4)
-; CHECK-NEXT: std 14, 224(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 15, 232(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 14, 416(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 15, 424(1) # 8-byte Folded Spill
+; CHECK-NEXT: stxv 52, 224(1) # 16-byte Folded Spill
+; CHECK-NEXT: stxv 53, 240(1) # 16-byte Folded Spill
+; CHECK-NEXT: stxv 54, 256(1) # 16-byte Folded Spill
+; CHECK-NEXT: std 16, 432(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 17, 440(1) # 8-byte Folded Spill
+; CHECK-NEXT: stxv 55, 272(1) # 16-byte Folded Spill
+; CHECK-NEXT: std 18, 448(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 19, 456(1) # 8-byte Folded Spill
+; CHECK-NEXT: stxv 56, 288(1) # 16-byte Folded Spill
+; CHECK-NEXT: stxv 57, 304(1) # 16-byte Folded Spill
+; CHECK-NEXT: std 20, 464(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 21, 472(1) # 8-byte Folded Spill
+; CHECK-NEXT: stxv 58, 320(1) # 16-byte Folded Spill
+; CHECK-NEXT: std 22, 480(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 23, 488(1) # 8-byte Folded Spill
+; CHECK-NEXT: stxv 59, 336(1) # 16-byte Folded Spill
+; CHECK-NEXT: stxv 60, 352(1) # 16-byte Folded Spill
+; CHECK-NEXT: std 24, 496(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 25, 504(1) # 8-byte Folded Spill
+; CHECK-NEXT: stxv 61, 368(1) # 16-byte Folded Spill
+; CHECK-NEXT: std 26, 512(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 27, 520(1) # 8-byte Folded Spill
+; CHECK-NEXT: stxv 62, 384(1) # 16-byte Folded Spill
+; CHECK-NEXT: stxv 63, 400(1) # 16-byte Folded Spill
+; CHECK-NEXT: std 28, 528(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 29, 536(1) # 8-byte Folded Spill
; CHECK-NEXT: cmpwi 4, 1
-; CHECK-NEXT: std 16, 240(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 17, 248(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 18, 256(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 19, 264(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 20, 272(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 21, 280(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 22, 288(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 23, 296(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 24, 304(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 25, 312(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 26, 320(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 27, 328(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 28, 336(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 29, 344(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 30, 352(1) # 8-byte Folded Spill
-; CHECK-NEXT: std 31, 360(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 18, 368(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 19, 376(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 20, 384(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 21, 392(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 22, 400(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 23, 408(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 24, 416(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 25, 424(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 26, 432(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 27, 440(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 28, 448(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 29, 456(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 30, 464(1) # 8-byte Folded Spill
-; CHECK-NEXT: stfd 31, 472(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 30, 544(1) # 8-byte Folded Spill
+; CHECK-NEXT: std 31, 552(1) # 8-byte Folded Spill
+; CHECK-NEXT: stfd 30, 560(1) # 8-byte Folded Spill
+; CHECK-NEXT: stfd 31, 568(1) # 8-byte Folded Spill
; CHECK-NEXT: blt 0, .LBB0_7
; CHECK-NEXT: # %bb.1: # %_loop_1_do_.lr.ph
; CHECK-NEXT: mr 23, 5
@@ -87,39 +87,39 @@ define void @foo(i32* %.m, i32* %.n, [0 x %_elem_type_of_a]* %.a, [0 x %_elem_ty
; CHECK-NEXT: # %bb.2: # %_loop_1_do_.preheader
; CHECK-NEXT: addi 5, 5, 1
; CHECK-NEXT: li 20, 9
-; CHECK-NEXT: ld 28, 728(1)
-; CHECK-NEXT: ld 19, 616(1)
+; CHECK-NEXT: ld 28, 824(1)
+; CHECK-NEXT: ld 19, 712(1)
; CHECK-NEXT: lwa 3, 0(7)
-; CHECK-NEXT: ld 7, 688(1)
-; CHECK-NEXT: ld 12, 680(1)
-; CHECK-NEXT: ld 11, 672(1)
-; CHECK-NEXT: ld 2, 664(1)
-; CHECK-NEXT: ld 29, 736(1)
+; CHECK-NEXT: ld 7, 784(1)
+; CHECK-NEXT: ld 12, 776(1)
+; CHECK-NEXT: ld 11, 768(1)
+; CHECK-NEXT: ld 2, 760(1)
+; CHECK-NEXT: ld 29, 832(1)
; CHECK-NEXT: cmpldi 5, 9
-; CHECK-NEXT: ld 27, 720(1)
-; CHECK-NEXT: ld 26, 712(1)
-; CHECK-NEXT: ld 25, 704(1)
-; CHECK-NEXT: ld 24, 696(1)
+; CHECK-NEXT: ld 27, 816(1)
+; CHECK-NEXT: ld 26, 808(1)
+; CHECK-NEXT: ld 25, 800(1)
+; CHECK-NEXT: ld 24, 792(1)
; CHECK-NEXT: iselgt 5, 5, 20
-; CHECK-NEXT: ld 30, 656(1)
-; CHECK-NEXT: ld 22, 648(1)
-; CHECK-NEXT: ld 21, 640(1)
-; CHECK-NEXT: ld 20, 632(1)
-; CHECK-NEXT: ld 18, 608(1)
-; CHECK-NEXT: ld 17, 600(1)
-; CHECK-NEXT: ld 16, 592(1)
-; CHECK-NEXT: ld 14, 584(1)
+; CHECK-NEXT: ld 30, 752(1)
+; CHECK-NEXT: ld 22, 744(1)
+; CHECK-NEXT: ld 21, 736(1)
+; CHECK-NEXT: ld 20, 728(1)
+; CHECK-NEXT: ld 18, 704(1)
+; CHECK-NEXT: ld 17, 696(1)
+; CHECK-NEXT: ld 16, 688(1)
+; CHECK-NEXT: ld 14, 680(1)
; CHECK-NEXT: sldi 0, 3, 2
; CHECK-NEXT: std 5, 216(1) # 8-byte Folded Spill
; CHECK-NEXT: std 28, 208(1) # 8-byte Folded Spill
; CHECK-NEXT: mr 5, 4
-; CHECK-NEXT: ld 4, 624(1)
+; CHECK-NEXT: ld 4, 720(1)
; CHECK-NEXT: std 19, 96(1) # 8-byte Folded Spill
; CHECK-NEXT: std 4, 104(1) # 8-byte Folded Spill
; CHECK-NEXT: lxv 11, 0(4)
; CHECK-NEXT: mr 4, 5
; CHECK-NEXT: ld 5, 216(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 15, 576(1)
+; CHECK-NEXT: ld 15, 672(1)
; CHECK-NEXT: sldi 31, 3, 1
; CHECK-NEXT: std 8, 32(1) # 8-byte Folded Spill
; CHECK-NEXT: std 9, 40(1) # 8-byte Folded Spill
@@ -221,13 +221,13 @@ define void @foo(i32* %.m, i32* %.n, [0 x %_elem_type_of_a]* %.a, [0 x %_elem_ty
; CHECK-NEXT: lxvp 46, 0(17)
; CHECK-NEXT: lxvp 48, 0(18)
; CHECK-NEXT: lxvp 50, 0(19)
-; CHECK-NEXT: lxvp 30, 0(20)
-; CHECK-NEXT: lxvp 28, 0(21)
-; CHECK-NEXT: lxvp 26, 32(6)
-; CHECK-NEXT: lxvp 24, 32(16)
-; CHECK-NEXT: lxvp 22, 32(17)
-; CHECK-NEXT: lxvp 20, 32(18)
-; CHECK-NEXT: lxvp 18, 32(19)
+; CHECK-NEXT: lxvp 62, 0(20)
+; CHECK-NEXT: lxvp 60, 0(21)
+; CHECK-NEXT: lxvp 58, 32(6)
+; CHECK-NEXT: lxvp 56, 32(16)
+; CHECK-NEXT: lxvp 54, 32(17)
+; CHECK-NEXT: lxvp 52, 32(18)
+; CHECK-NEXT: lxvp 30, 32(19)
; CHECK-NEXT: addi 6, 6, 64
; CHECK-NEXT: addi 16, 16, 64
; CHECK-NEXT: addi 17, 17, 64
@@ -237,30 +237,30 @@ define void @foo(i32* %.m, i32* %.n, [0 x %_elem_type_of_a]* %.a, [0 x %_elem_ty
; CHECK-NEXT: xvmaddadp 40, 47, 43
; CHECK-NEXT: xvmaddadp 39, 49, 43
; CHECK-NEXT: xvmaddadp 38, 51, 43
-; CHECK-NEXT: xvmaddadp 33, 31, 43
-; CHECK-NEXT: xvmaddadp 32, 29, 43
+; CHECK-NEXT: xvmaddadp 33, 63, 43
+; CHECK-NEXT: xvmaddadp 32, 61, 43
; CHECK-NEXT: xvmaddadp 37, 44, 42
; CHECK-NEXT: xvmaddadp 35, 46, 42
; CHECK-NEXT: xvmaddadp 13, 48, 42
; CHECK-NEXT: xvmaddadp 11, 50, 42
-; CHECK-NEXT: xvmaddadp 10, 30, 42
-; CHECK-NEXT: xvmaddadp 8, 28, 42
+; CHECK-NEXT: xvmaddadp 10, 62, 42
+; CHECK-NEXT: xvmaddadp 8, 60, 42
; CHECK-NEXT: lxvp 42, 32(20)
; CHECK-NEXT: lxvp 44, 32(21)
; CHECK-NEXT: addi 20, 20, 64
; CHECK-NEXT: addi 21, 21, 64
-; CHECK-NEXT: xvmaddadp 6, 25, 27
-; CHECK-NEXT: xvmaddadp 4, 23, 27
-; CHECK-NEXT: xvmaddadp 3, 21, 27
-; CHECK-NEXT: xvmaddadp 2, 19, 27
-; CHECK-NEXT: xvmaddadp 36, 24, 26
-; CHECK-NEXT: xvmaddadp 34, 22, 26
-; CHECK-NEXT: xvmaddadp 12, 20, 26
-; CHECK-NEXT: xvmaddadp 9, 18, 26
-; CHECK-NEXT: xvmaddadp 1, 43, 27
-; CHECK-NEXT: xvmaddadp 0, 45, 27
-; CHECK-NEXT: xvmaddadp 7, 42, 26
-; CHECK-NEXT: xvmaddadp 5, 44, 26
+; CHECK-NEXT: xvmaddadp 6, 57, 59
+; CHECK-NEXT: xvmaddadp 4, 55, 59
+; CHECK-NEXT: xvmaddadp 3, 53, 59
+; CHECK-NEXT: xvmaddadp 2, 31, 59
+; CHECK-NEXT: xvmaddadp 36, 56, 58
+; CHECK-NEXT: xvmaddadp 34, 54, 58
+; CHECK-NEXT: xvmaddadp 12, 52, 58
+; CHECK-NEXT: xvmaddadp 9, 30, 58
+; CHECK-NEXT: xvmaddadp 1, 43, 59
+; CHECK-NEXT: xvmaddadp 0, 45, 59
+; CHECK-NEXT: xvmaddadp 7, 42, 58
+; CHECK-NEXT: xvmaddadp 5, 44, 58
; CHECK-NEXT: bdnz .LBB0_4
; CHECK-NEXT: # %bb.5: # %_loop_2_endl_
; CHECK-NEXT: #
@@ -324,39 +324,39 @@ define void @foo(i32* %.m, i32* %.n, [0 x %_elem_type_of_a]* %.a, [0 x %_elem_ty
; CHECK-NEXT: ld 3, 216(1) # 8-byte Folded Reload
; CHECK-NEXT: stxv 5, 0(3)
; CHECK-NEXT: .LBB0_7: # %_return_bb
-; CHECK-NEXT: lfd 31, 472(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 30, 464(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 31, 360(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 30, 352(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 29, 344(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 28, 336(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 27, 328(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 26, 320(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 25, 312(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 29, 456(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 24, 304(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 23, 296(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 22, 288(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 28, 448(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 21, 280(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 20, 272(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 19, 264(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 27, 440(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 18, 256(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 17, 248(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 16, 240(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 26, 432(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 15, 232(1) # 8-byte Folded Reload
-; CHECK-NEXT: ld 14, 224(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 25, 424(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 24, 416(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 23, 408(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 22, 400(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 21, 392(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 20, 384(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 19, 376(1) # 8-byte Folded Reload
-; CHECK-NEXT: lfd 18, 368(1) # 8-byte Folded Reload
-; CHECK-NEXT: addi 1, 1, 480
+; CHECK-NEXT: lxv 63, 400(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 62, 384(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 61, 368(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 60, 352(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 59, 336(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 58, 320(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 57, 304(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 56, 288(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 55, 272(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 54, 256(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 53, 240(1) # 16-byte Folded Reload
+; CHECK-NEXT: lxv 52, 224(1) # 16-byte Folded Reload
+; CHECK-NEXT: lfd 31, 568(1) # 8-byte Folded Reload
+; CHECK-NEXT: lfd 30, 560(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 31, 552(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 30, 544(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 29, 536(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 28, 528(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 27, 520(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 26, 512(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 25, 504(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 24, 496(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 23, 488(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 22, 480(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 21, 472(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 20, 464(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 19, 456(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 18, 448(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 17, 440(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 16, 432(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 15, 424(1) # 8-byte Folded Reload
+; CHECK-NEXT: ld 14, 416(1) # 8-byte Folded Reload
+; CHECK-NEXT: addi 1, 1, 576
; CHECK-NEXT: blr
entry:
%_val_l_ = load i32, i32* %.l, align 4
diff --git a/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll b/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
index c92eed92d0531..9ebc89f79cae8 100644
--- a/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -20,34 +20,30 @@ declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
; CHECK-LABEL: ass_pair:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor vs1, v2, v2
-; CHECK-NEXT: xxlor vs0, vs1, vs1
-; CHECK-NEXT: stxv vs1, 16(r3)
-; CHECK-NEXT: stxv vs1, 0(r3)
+; CHECK-NEXT: vmr v3, v2
+; CHECK-NEXT: stxv v2, 16(r3)
+; CHECK-NEXT: stxv v3, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: ass_pair:
; CHECK-NOMMA: # %bb.0: # %entry
-; CHECK-NOMMA-NEXT: xxlor vs1, v2, v2
-; CHECK-NOMMA-NEXT: xxlor vs0, vs1, vs1
-; CHECK-NOMMA-NEXT: stxv vs1, 16(r3)
-; CHECK-NOMMA-NEXT: stxv vs1, 0(r3)
+; CHECK-NOMMA-NEXT: vmr v3, v2
+; CHECK-NOMMA-NEXT: stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT: stxv v3, 0(r3)
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: ass_pair:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxlor vs1, v2, v2
-; CHECK-BE-NEXT: xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT: stxv vs1, 16(r3)
-; CHECK-BE-NEXT: stxv vs0, 0(r3)
+; CHECK-BE-NEXT: vmr v3, v2
+; CHECK-BE-NEXT: stxv v2, 16(r3)
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: ass_pair:
; CHECK-BE-NOMMA: # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT: xxlor vs1, v2, v2
-; CHECK-BE-NOMMA-NEXT: xxlor vs0, vs1, vs1
-; CHECK-BE-NOMMA-NEXT: stxv vs1, 16(r3)
-; CHECK-BE-NOMMA-NEXT: stxv vs0, 0(r3)
+; CHECK-BE-NOMMA-NEXT: vmr v3, v2
+; CHECK-BE-NOMMA-NEXT: stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT: stxv v2, 0(r3)
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
@@ -60,34 +56,34 @@ declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
; CHECK-LABEL: disass_pair:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv vs1, 0(r3)
-; CHECK-NEXT: lxv vs0, 16(r3)
-; CHECK-NEXT: stxv vs1, 0(r4)
-; CHECK-NEXT: stxv vs0, 0(r5)
+; CHECK-NEXT: lxv v3, 0(r3)
+; CHECK-NEXT: lxv v2, 16(r3)
+; CHECK-NEXT: stxv v3, 0(r4)
+; CHECK-NEXT: stxv v2, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: disass_pair:
; CHECK-NOMMA: # %bb.0: # %entry
-; CHECK-NOMMA-NEXT: lxv vs1, 0(r3)
-; CHECK-NOMMA-NEXT: lxv vs0, 16(r3)
-; CHECK-NOMMA-NEXT: stxv vs1, 0(r4)
-; CHECK-NOMMA-NEXT: stxv vs0, 0(r5)
+; CHECK-NOMMA-NEXT: lxv v3, 0(r3)
+; CHECK-NOMMA-NEXT: lxv v2, 16(r3)
+; CHECK-NOMMA-NEXT: stxv v3, 0(r4)
+; CHECK-NOMMA-NEXT: stxv v2, 0(r5)
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: disass_pair:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxv vs1, 16(r3)
-; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: stxv vs0, 0(r4)
-; CHECK-BE-NEXT: stxv vs1, 0(r5)
+; CHECK-BE-NEXT: lxv v3, 16(r3)
+; CHECK-BE-NEXT: lxv v2, 0(r3)
+; CHECK-BE-NEXT: stxv v2, 0(r4)
+; CHECK-BE-NEXT: stxv v3, 0(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: disass_pair:
; CHECK-BE-NOMMA: # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT: lxv vs1, 16(r3)
-; CHECK-BE-NOMMA-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NOMMA-NEXT: stxv vs0, 0(r4)
-; CHECK-BE-NOMMA-NEXT: stxv vs1, 0(r5)
+; CHECK-BE-NOMMA-NEXT: lxv v3, 16(r3)
+; CHECK-BE-NOMMA-NEXT: lxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT: stxv v2, 0(r4)
+; CHECK-BE-NOMMA-NEXT: stxv v3, 0(r5)
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
@@ -102,26 +98,26 @@ entry:
define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
; CHECK-LABEL: test_ldst_1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxvp vsp0, 0(r3)
-; CHECK-NEXT: stxvp vsp0, 0(r4)
+; CHECK-NEXT: lxvp vsp34, 0(r3)
+; CHECK-NEXT: stxvp vsp34, 0(r4)
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: test_ldst_1:
; CHECK-NOMMA: # %bb.0: # %entry
-; CHECK-NOMMA-NEXT: lxvp vsp0, 0(r3)
-; CHECK-NOMMA-NEXT: stxvp vsp0, 0(r4)
+; CHECK-NOMMA-NEXT: lxvp vsp34, 0(r3)
+; CHECK-NOMMA-NEXT: stxvp vsp34, 0(r4)
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: test_ldst_1:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxvp vsp0, 0(r3)
-; CHECK-BE-NEXT: stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp34, 0(r3)
+; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: test_ldst_1:
; CHECK-BE-NOMMA: # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT: lxvp vsp0, 0(r3)
-; CHECK-BE-NOMMA-NEXT: stxvp vsp0, 0(r4)
+; CHECK-BE-NOMMA-NEXT: lxvp vsp34, 0(r3)
+; CHECK-BE-NOMMA-NEXT: stxvp vsp34, 0(r4)
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = bitcast <256 x i1>* %vpp to i8*
@@ -137,26 +133,26 @@ declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
; CHECK-LABEL: test_ldst_2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxvpx vsp0, r3, r4
-; CHECK-NEXT: stxvpx vsp0, r5, r4
+; CHECK-NEXT: lxvpx vsp34, r3, r4
+; CHECK-NEXT: stxvpx vsp34, r5, r4
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: test_ldst_2:
; CHECK-NOMMA: # %bb.0: # %entry
-; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r4
-; CHECK-NOMMA-NEXT: stxvpx vsp0, r5, r4
+; CHECK-NOMMA-NEXT: lxvpx vsp34, r3, r4
+; CHECK-NOMMA-NEXT: stxvpx vsp34, r5, r4
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: test_ldst_2:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxvpx vsp0, r3, r4
-; CHECK-BE-NEXT: stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT: lxvpx vsp34, r3, r4
+; CHECK-BE-NEXT: stxvpx vsp34, r5, r4
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: test_ldst_2:
; CHECK-BE-NOMMA: # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r4
-; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r5, r4
+; CHECK-BE-NOMMA-NEXT: lxvpx vsp34, r3, r4
+; CHECK-BE-NOMMA-NEXT: stxvpx vsp34, r5, r4
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = bitcast <256 x i1>* %vpp to i8*
@@ -172,29 +168,29 @@ define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
; CHECK-LABEL: test_ldst_3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r5, 18
-; CHECK-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NEXT: stxvpx vsp34, r4, r5
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: test_ldst_3:
; CHECK-NOMMA: # %bb.0: # %entry
; CHECK-NOMMA-NEXT: li r5, 18
-; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: test_ldst_3:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: li r5, 18
-; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: test_ldst_3:
; CHECK-BE-NOMMA: # %bb.0: # %entry
; CHECK-BE-NOMMA-NEXT: li r5, 18
-; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = bitcast <256 x i1>* %vpp to i8*
@@ -210,29 +206,29 @@ define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
; CHECK-LABEL: test_ldst_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r5, 1
-; CHECK-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NEXT: stxvpx vsp34, r4, r5
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: test_ldst_4:
; CHECK-NOMMA: # %bb.0: # %entry
; CHECK-NOMMA-NEXT: li r5, 1
-; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: test_ldst_4:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: li r5, 1
-; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: test_ldst_4:
; CHECK-BE-NOMMA: # %bb.0: # %entry
; CHECK-BE-NOMMA-NEXT: li r5, 1
-; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = bitcast <256 x i1>* %vpp to i8*
@@ -248,29 +244,29 @@ define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
; CHECK-LABEL: test_ldst_5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r5, 42
-; CHECK-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NEXT: stxvpx vsp34, r4, r5
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: test_ldst_5:
; CHECK-NOMMA: # %bb.0: # %entry
; CHECK-NOMMA-NEXT: li r5, 42
-; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: test_ldst_5:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: li r5, 42
-; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: test_ldst_5:
; CHECK-BE-NOMMA: # %bb.0: # %entry
; CHECK-BE-NOMMA-NEXT: li r5, 42
-; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = bitcast <256 x i1>* %vpp to i8*
@@ -285,26 +281,26 @@ entry:
define void @test_ldst_6(<256 x i1>* %vpp, <256 x i1>* %vp2) {
; CHECK-LABEL: test_ldst_6:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxvp vsp0, 4096(r3)
-; CHECK-NEXT: stxvp vsp0, 4096(r4)
+; CHECK-NEXT: lxvp vsp34, 4096(r3)
+; CHECK-NEXT: stxvp vsp34, 4096(r4)
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: test_ldst_6:
; CHECK-NOMMA: # %bb.0: # %entry
-; CHECK-NOMMA-NEXT: lxvp vsp0, 4096(r3)
-; CHECK-NOMMA-NEXT: stxvp vsp0, 4096(r4)
+; CHECK-NOMMA-NEXT: lxvp vsp34, 4096(r3)
+; CHECK-NOMMA-NEXT: stxvp vsp34, 4096(r4)
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: test_ldst_6:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxvp vsp0, 4096(r3)
-; CHECK-BE-NEXT: stxvp vsp0, 4096(r4)
+; CHECK-BE-NEXT: lxvp vsp34, 4096(r3)
+; CHECK-BE-NEXT: stxvp vsp34, 4096(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: test_ldst_6:
; CHECK-BE-NOMMA: # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT: lxvp vsp0, 4096(r3)
-; CHECK-BE-NOMMA-NEXT: stxvp vsp0, 4096(r4)
+; CHECK-BE-NOMMA-NEXT: lxvp vsp34, 4096(r3)
+; CHECK-BE-NOMMA-NEXT: stxvp vsp34, 4096(r4)
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = getelementptr <256 x i1>, <256 x i1>* %vpp, i64 128
@@ -322,29 +318,29 @@ define void @test_ldst_7(<256 x i1>* %vpp, <256 x i1>* %vp2) {
; CHECK-LABEL: test_ldst_7:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pli r5, 32799
-; CHECK-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NEXT: stxvpx vsp34, r4, r5
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: test_ldst_7:
; CHECK-NOMMA: # %bb.0: # %entry
; CHECK-NOMMA-NEXT: pli r5, 32799
-; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: test_ldst_7:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pli r5, 32799
-; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: test_ldst_7:
; CHECK-BE-NOMMA: # %bb.0: # %entry
; CHECK-BE-NOMMA-NEXT: pli r5, 32799
-; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT: lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT: stxvpx vsp34, r4, r5
; CHECK-BE-NOMMA-NEXT: blr
entry:
%0 = bitcast <256 x i1>* %vpp to i8*
diff --git a/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll b/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll
index 31043e6fee138..dcede94054cbf 100644
--- a/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll
+++ b/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll
@@ -39,13 +39,13 @@ define dso_local void @test(<256 x i1>* %vpp, <256 x i1>* %vp2) local_unnamed_ad
; CHECK-NEXT: stxv v31, 240(r1) # 16-byte Folded Spill
; CHECK-NEXT: stfd f30, 384(r1) # 8-byte Folded Spill
; CHECK-NEXT: stfd f31, 392(r1) # 8-byte Folded Spill
-; CHECK-NEXT: lxvp vsp0, 0(r3)
-; CHECK-NEXT: stxvp vsp0, 32(r1) # 32-byte Folded Spill
+; CHECK-NEXT: lxvp vsp34, 0(r3)
+; CHECK-NEXT: stxvp vsp34, 32(r1) # 32-byte Folded Spill
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: lxvp vsp0, 32(r1) # 32-byte Folded Reload
-; CHECK-NEXT: stxvp vsp0, 0(r4)
+; CHECK-NEXT: lxvp vsp34, 32(r1) # 32-byte Folded Reload
+; CHECK-NEXT: stxvp vsp34, 0(r4)
; CHECK-NEXT: lxv v31, 240(r1) # 16-byte Folded Reload
; CHECK-NEXT: lxv v30, 224(r1) # 16-byte Folded Reload
; CHECK-NEXT: lxv v29, 208(r1) # 16-byte Folded Reload
@@ -112,13 +112,13 @@ define dso_local void @test(<256 x i1>* %vpp, <256 x i1>* %vp2) local_unnamed_ad
; CHECK-BE-NEXT: stxv v31, 256(r1) # 16-byte Folded Spill
; CHECK-BE-NEXT: stfd f30, 400(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: stfd f31, 408(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT: lxvp vsp0, 0(r3)
-; CHECK-BE-NEXT: stxvp vsp0, 48(r1) # 32-byte Folded Spill
+; CHECK-BE-NEXT: lxvp vsp34, 0(r3)
+; CHECK-BE-NEXT: stxvp vsp34, 48(r1) # 32-byte Folded Spill
; CHECK-BE-NEXT: #APP
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: #NO_APP
-; CHECK-BE-NEXT: lxvp vsp0, 48(r1) # 32-byte Folded Reload
-; CHECK-BE-NEXT: stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp34, 48(r1) # 32-byte Folded Reload
+; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
; CHECK-BE-NEXT: lxv v31, 256(r1) # 16-byte Folded Reload
; CHECK-BE-NEXT: lxv v30, 240(r1) # 16-byte Folded Reload
; CHECK-BE-NEXT: lxv v29, 224(r1) # 16-byte Folded Reload
More information about the llvm-commits
mailing list