[PATCH] D103408: Teach peephole optimizer to not emit sub-register defs

[Ahsan Saghir via Phabricator via llvm-commits]

saghir marked 3 inline comments as done.
saghir added inline comments.


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Comment at: llvm/lib/CodeGen/PeepholeOptimizer.cpp:593
+      //
+      if (UseSrcSubIdx && (UseMI->getOpcode() == TargetOpcode::COPY)) {
+        UseSrcSubIdx = false;
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arsenm wrote:
> I don't see why you need to special case the use opcode
Thanks, you are right, it is not really needed. I have removed the check for the opcode. I have also refined the approach to handle the case for when `UseSrcSubIdx` is `true`.


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Comment at: llvm/lib/CodeGen/PeepholeOptimizer.cpp:612
                                    TII->get(TargetOpcode::COPY), NewVR)
         .addReg(DstReg, 0, SubIdx);
       // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
----------------
arsenm wrote:
> The SubIdx should not be passed through here?
I think, we need to copy 32-bit subreg value from the 64-bit register.  So we need to generate something like this:
`%6:gprc_and_gprc_nor0 = COPY %1.sub_32:g8rc_and_g8rc_nox0`

Removing SubIdx, leads to copying the complete 64-bit register and we end up generating: 
`%6:gprc_and_gprc_nor0 = COPY %1:g8rc_and_g8rc_nox0`

which does not look right, unless I am missing something here.


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Comment at: llvm/test/CodeGen/PowerPC/peephole-subreg.mir:5-30
+--- |
+  declare i64 @strlen() local_unnamed_addr
+
+  define dso_local fastcc void @check_format_info_main() unnamed_addr {
+  entry:
+    %0 = zext i8 undef to i32
+    %cond = icmp eq i32 %0, 0
----------------
arsenm wrote:
> IR section is not necessary
I have simplified the IR to generate the test case. However, removing the IR section, gives me error for `use of undefined global value '@strlen'`.


Repository:
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  https://reviews.llvm.org/D103408/new/

https://reviews.llvm.org/D103408