[PATCH] D104853: [X86] Add description of FXAM instruction
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 24 15:37:19 PDT 2021
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
AMD's optimization manual for bulldozer only shows a 2 cycle latency. I'm not sure why Agner reports 20 unless there's some bad case for some particular input that isn't documented. A single uop taking 20 cycles sounds very strange and must be serializing the machine. I would only expect divide/sqrt to be that high from a single uop. Maybe someone can run llvm-exegesis and one of those AMD CPUs
This patch seems ok since it doesn't change codegen.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D104853/new/
https://reviews.llvm.org/D104853
More information about the llvm-commits
mailing list