[llvm] 571c8c5 - [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
Pablo Barrio via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 24 10:25:00 PDT 2021
Author: Pablo Barrio
Date: 2021-06-24T18:24:32+01:00
New Revision: 571c8c5263a79293aaadae07b11feb36726eaf53
URL: https://github.com/llvm/llvm-project/commit/571c8c5263a79293aaadae07b11feb36726eaf53
DIFF: https://github.com/llvm/llvm-project/commit/571c8c5263a79293aaadae07b11feb36726eaf53.diff
LOG: [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
PACI*SP have the advantage that they are in HINT space, meaning
they can be run successfully in hardware without PAuth support -
they will just behave as a NOP. However, PACI*SP are also implicit
landing pads (think of an extra BTI jc). Therefore, they allow
indirect jumps of all kinds into them, potentially inserting new
gadgets. This patch replaces PACI*SP by PACI* LR, SP when
compiling explicitly for hardware with full PAuth support. PACI*
is not in the HINT space, therefore it will fault when run in
hardware without PAuth support, but it is also not a landing pad,
making programs safer in newer HW.
Differential Revision: https://reviews.llvm.org/D101920
Added:
Modified:
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll
llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
llvm/test/CodeGen/AArch64/sign-return-address.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 7ef3007c9791..9d318d8f5e9b 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -1129,16 +1129,23 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
const auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
if (MFnI.shouldSignReturnAddress()) {
+
+ unsigned PACI;
if (MFnI.shouldSignWithBKey()) {
BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY))
.setMIFlag(MachineInstr::FrameSetup);
- BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIBSP))
- .setMIFlag(MachineInstr::FrameSetup);
+ PACI = Subtarget.hasPAuth() ? AArch64::PACIB : AArch64::PACIBSP;
} else {
- BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP))
- .setMIFlag(MachineInstr::FrameSetup);
+ PACI = Subtarget.hasPAuth() ? AArch64::PACIA : AArch64::PACIASP;
}
+ auto MI = BuildMI(MBB, MBBI, DL, TII->get(PACI));
+ if (Subtarget.hasPAuth())
+ MI.addReg(AArch64::LR, RegState::Define)
+ .addReg(AArch64::LR)
+ .addReg(AArch64::SP, RegState::InternalRead);
+ MI.setMIFlag(MachineInstr::FrameSetup);
+
unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index a8a0b6d375d5..0f2e7c4cd09b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -7132,15 +7132,22 @@ static void signOutlinedFunction(MachineFunction &MF, MachineBasicBlock &MBB,
// PACIASP EMITBKEY
// CFI_INSTRUCTION PACIBSP
// CFI_INSTRUCTION
+ unsigned PACI;
if (ShouldSignReturnAddrWithAKey) {
- BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIASP))
- .setMIFlag(MachineInstr::FrameSetup);
+ PACI = Subtarget.hasPAuth() ? AArch64::PACIA : AArch64::PACIASP;
} else {
BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::EMITBKEY))
.setMIFlag(MachineInstr::FrameSetup);
- BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIBSP))
- .setMIFlag(MachineInstr::FrameSetup);
+ PACI = Subtarget.hasPAuth() ? AArch64::PACIB : AArch64::PACIBSP;
}
+
+ auto MI = BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(PACI));
+ if (Subtarget.hasPAuth())
+ MI.addReg(AArch64::LR, RegState::Define)
+ .addReg(AArch64::LR)
+ .addReg(AArch64::SP, RegState::InternalRead);
+ MI.setMIFlag(MachineInstr::FrameSetup);
+
unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::CFI_INSTRUCTION))
diff --git a/llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll b/llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
index f7488d874fd1..12a4939e9e52 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
-; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; Armv8.3-A Pointer Authetication requires a special instruction to strip the
; pointer authentication code from the pointer.
; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
@@ -34,7 +34,7 @@ entry:
; CHECK-NEXT: ldr x30, [sp], #16
; CHECK-NEXT: hint #29
; CHECK-NEXT: ret
-; CHECKV83: paciasp
+; CHECKV83: pacia x30, sp
; CHECKV83-NEXT: str x30, [sp, #-16]!
; CHECKV83-NEXT: xpaci x30
; CHECKV83-NEXT: mov x0, x30
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
index 8fd152869b23..540fa1c46dd6 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
@@ -5,7 +5,7 @@
; CHECK-LABEL: foo: // @foo
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: paciasp
+; CHECK-NEXT: pacia x30, sp
; CHECK-NOT: OUTLINED_FUNCTION_
; CHECK: retaa
define dso_local void @foo(i32 %x) #0 {
@@ -23,7 +23,7 @@ entry:
; CHECK-LABEL: bar: // @bar
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: paciasp
+; CHECK-NEXT: pacia x30, sp
; CHECK-NOT: OUTLINED_FUNCTION_
; CHECK: retaa
define dso_local void @bar(i32 %x) #0 {
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
index 1459b62ee0f3..8e8538957924 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
@@ -9,7 +9,7 @@ define void @a() #0 {
; CHECK-LABEL: a: // @a
; CHECK: // %bb.0:
; CHECK-NEXT: .cfi_b_key_frame
-; CHECK-NEXT: pacibsp
+; CHECK-NEXT: pacib x30, sp
; CHECK-NEXT: .cfi_negate_ra_state
; CHECK-NOT: OUTLINED_FUNCTION_
%1 = alloca i32, align 4
@@ -33,7 +33,7 @@ define void @b() #0 {
; CHECK-LABEL: b: // @b
; CHECK: // %bb.0:
; CHECK-NEXT: .cfi_b_key_frame
-; CHECK-NEXT: pacibsp
+; CHECK-NEXT: pacib x30, sp
; CHECK-NEXT: .cfi_negate_ra_state
; CHECK-NOT: OUTLINED_FUNCTION_
%1 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll
index 2c66bcb6f4e0..3837aa58f8a3 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll
@@ -7,7 +7,7 @@
define void @a() #0 {
; CHECK-LABEL: a: // @a
; CHECK: // %bb.0:
-; CHECK-NEXT: pacibsp
+; CHECK-NEXT: pacib x30, sp
; CHECK: bl [[OUTLINED_FUNC:OUTLINED_FUNCTION_[0-9]+]]
%1 = alloca i32, align 4
%2 = alloca i32, align 4
@@ -22,14 +22,14 @@ define void @a() #0 {
store i32 5, i32* %5, align 4
store i32 6, i32* %6, align 4
; CHECK: retab
-; CHECK-NOT: auti[a,b]sp
+; CHECK-NOT: auti
ret void
}
define void @b() #0 {
; CHECK-LABEL: b: // @b
; CHECK: // %bb.0:
-; CHECK-NEXT: pacibsp
+; CHECK-NEXT: pacib x30, sp
; CHECK: bl OUTLINED_FUNC
%1 = alloca i32, align 4
%2 = alloca i32, align 4
@@ -44,14 +44,14 @@ define void @b() #0 {
store i32 5, i32* %5, align 4
store i32 6, i32* %6, align 4
; CHECK: retab
-; CHECK-NOT: auti[a,b]sp
+; CHECK-NOT: auti
ret void
}
define void @c() #0 {
; CHECK-LABEL: c: // @c
; CHECK: // %bb.0:
-; CHECK-NEXT: pacibsp
+; CHECK-NEXT: pacib x30, sp
; CHECK: bl OUTLINED_FUNC
%1 = alloca i32, align 4
%2 = alloca i32, align 4
@@ -66,7 +66,7 @@ define void @c() #0 {
store i32 5, i32* %5, align 4
store i32 6, i32* %6, align 4
; CHECK: retab
-; CHECK-NOT: auti[a,b]sp
+; CHECK-NOT: auti
ret void
}
@@ -77,6 +77,6 @@ attributes #0 = { "sign-return-address"="all"
; CHECK: OUTLINED_FUNC
; CHECK: // %bb.0:
-; CHECK-NEXT: pacibsp
+; CHECK-NEXT: pacib x30, sp
; CHECK: retab
; CHECK-NOT: auti[a,b]sp
diff --git a/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll b/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
index b302a3d55add..e8c659380f7c 100644
--- a/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
+++ b/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
@@ -11,7 +11,7 @@ entry:
ret i32 0
}
;; CHECK-LABEL: f:
-;; CHECK: pacibsp
+;; CHECK: pacib x30, sp
declare void @llvm_gcda_start_file(i8*, i32, i32) local_unnamed_addr
@@ -34,7 +34,7 @@ entry:
}
;; CHECK-LABEL: __llvm_gcov_writeout:
;; CHECK: .cfi_b_key_frame
-;; CHECK-NEXT: pacibsp
+;; CHECK-NEXT: pacib x30, sp
;; CHECK-NEXT: .cfi_negate_ra_state
define internal void @__llvm_gcov_reset() unnamed_addr #2 {
@@ -43,7 +43,7 @@ entry:
ret void
}
;; CHECK-LABEL: __llvm_gcov_reset:
-;; CHECK: pacibsp
+;; CHECK: pacib x30, sp
declare void @llvm_gcov_init(void ()*, void ()*) local_unnamed_addr
@@ -54,7 +54,7 @@ entry:
}
;; CHECK-LABEL: __llvm_gcov_init:
;; CHECK: .cfi_b_key_frame
-;; CHECK-NEXT: pacibsp
+;; CHECK-NEXT: pacib x30, sp
;; CHECK-NEXT: .cfi_negate_ra_state
attributes #0 = { norecurse nounwind readnone "sign-return-address"="all" "sign-return-address-key"="b_key" }
diff --git a/llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll b/llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
index 8fe20d5ebbb1..27287bd1895e 100644
--- a/llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
+++ b/llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
@@ -30,7 +30,7 @@ entry:
ret i32 %add
}
;; CHECK-LABEL: f2:
-;; CHECK: paciasp
+;; CHECK: pacia x30, sp
;; CHECK: retaa
define i32 @f3(i32 %x) #3 {
@@ -40,7 +40,7 @@ entry:
ret i32 %add
}
;; CHECK-LABEL: f3:
-;; CHECK: pacibsp
+;; CHECK: pacib x30, sp
;; CHECK: retab
define i32 @f4(i32 %x) #4 {
@@ -48,7 +48,7 @@ entry:
ret i32 1
}
;; CHECK-LABEL: f4:
-;; CHECK: paciasp
+;; CHECK: pacia x30, sp
;; CHECK: retaa
define i32 @f5(i32 %x) #5 {
@@ -58,7 +58,7 @@ entry:
ret i32 %add
}
;; CHECK-LABEL: f5:
-;; CHECK: paciasp
+;; CHECK: pacia x30, sp
;; CHECK: retaa
attributes #0 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="none" }
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
index 0dc7b24bca67..72ebf7161f78 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
@@ -7,7 +7,7 @@
; CHECK: @_Z3fooi
; CHECK-V8A: hint #25
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK-NEXT: .cfi_negate_ra_state
; CHECK-NOT: .cfi_negate_ra_state
define dso_local i32 @_Z3fooi(i32 %x) #0 {
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address.ll b/llvm/test/CodeGen/AArch64/sign-return-address.ll
index 68af27d01d76..498f82a00e98 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address.ll
@@ -26,7 +26,7 @@ define i32 @leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" {
; CHECK: hint #25
; CHECK: hint #29
; CHECK: ret
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK-V83A: retaa
define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" {
ret i32 %x
@@ -34,7 +34,7 @@ define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" {
; CHECK: @leaf_clobbers_lr
; CHECK: hint #25
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK, CHECK-V83A: str x30, [sp, #-16]!
; CHECK, CHECK-V83A: ldr x30, [sp], #16
; CHECK: hint #29
@@ -51,7 +51,7 @@ declare i32 @foo(i32)
; CHECK: hint #25
; CHECK: hint #29
; CHECK: ret
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK-V83A: retaa
define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
%call = call i32 @foo(i32 %x)
@@ -60,7 +60,7 @@ define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
; CHECK: @non_leaf_sign_non_leaf
; CHECK: hint #25
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK, CHECK-V83A: str x30, [sp, #-16]!
; CHECK, CHECK-V83A: ldr x30, [sp], #16
; CHECK: hint #29
@@ -72,7 +72,7 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" {
}
; CHECK-LABEL: @leaf_sign_all_v83
-; CHECK: paciasp
+; CHECK: pacia x30, sp
; CHECK-NOT: ret
; CHECK: retaa
; CHECK-NOT: ret
@@ -84,7 +84,7 @@ declare fastcc i64 @bar(i64)
; CHECK-LABEL: @spill_lr_and_tail_call
; CHECK: hint #25
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK, CHECK-V83A: str x30, [sp, #-16]!
; CHECK, CHECK-V83A: ldr x30, [sp], #16
; CHECK-V83A: autiasp
@@ -99,7 +99,7 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
; CHECK-LABEL: @leaf_sign_all_a_key
; CHECK: hint #25
; CHECK: hint #29
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK-V83A: retaa
define i32 @leaf_sign_all_a_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" {
ret i32 %x
@@ -108,14 +108,14 @@ define i32 @leaf_sign_all_a_key(i32 %x) "sign-return-address"="all" "sign-return
; CHECK-LABEL: @leaf_sign_all_b_key
; CHECK: hint #27
; CHECK: hint #31
-; CHECK-V83A: pacibsp
+; CHECK-V83A: pacib x30, sp
; CHECK-V83A: retab
define i32 @leaf_sign_all_b_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" {
ret i32 %x
}
; CHECK-LABEL: @leaf_sign_all_v83_b_key
-; CHECK: pacibsp
+; CHECK: pacib x30, sp
; CHECK-NOT: ret
; CHECK: retab
; CHECK-NOT: ret
@@ -127,7 +127,7 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "sign-return-address"="all" "target-
; CHECK-NOT: hint #34
; CHECK: hint #25
; CHECK: hint #29
-; CHECK-V83A: paciasp
+; CHECK-V83A: pacia x30, sp
; CHECK-V83A: retaa
define i32 @leaf_sign_all_a_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" "branch-target-enforcement"="true"{
ret i32 %x
@@ -137,15 +137,14 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "sign-return-address"="all" "sign-re
; CHECK-NOT: hint #34
; CHECK: hint #27
; CHECK: hint #31
-; CHECK-V83A: pacibsp
+; CHECK-V83A: pacib x30, sp
; CHECK-V83A: retab
define i32 @leaf_sign_all_b_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" "branch-target-enforcement"="true"{
ret i32 %x
}
; CHECK-LABEL: @leaf_sign_all_v83_b_key_bti
-; CHECK-NOT: hint #34
-; CHECK: pacibsp
+; CHECK: pacib x30, sp
; CHECK-NOT: ret
; CHECK: retab
; CHECK-NOT: ret
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