[PATCH] D104722: [SVE] Added CodeGen support for inserting an element into a predicate vector

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 24 09:19:34 PDT 2021


sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10154
+    SDValue ExtendedValue = DAG.getAnyExtOrTrunc(
+        Op.getOperand(1), DL, (VectorVT == MVT::nxv2i64) ? MVT::i64 : MVT::i32);
+    ExtendedVector =
----------------
nit:
  VectorVT.getScalarType().getSizeInBits() < 32 ? MVT::i32 : VectorVT.getScalarType()



================
Comment at: llvm/test/CodeGen/AArch64/sve-insert-element.ll:372
+; CHECK-NEXT:    cmpne p0.d, p1/z, z0.d, #0
+; CHECK-NEXT:    ret
+  %res = insertelement <vscale x 2 x i1> %val, i1 %elt, i32 %idx
----------------
efriedma wrote:
> This looks messy, but I guess it's actually a surprisingly hard operation to implement in the general case. I guess you might be able to save an instruction or two here, but probably can't get it a lot shorter.
> 
> Could you include a couple testcases where idx and/or elt are constants, just to get an idea what that looks like?
I'd expect this to be quite a rare operation in practice though, so probably not worth optimising early.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104722/new/

https://reviews.llvm.org/D104722



More information about the llvm-commits mailing list