[llvm] c74aea4 - [AArch64] Precommit extending load tests for D104782. NFC.
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 24 08:00:01 PDT 2021
Author: Sjoerd Meijer
Date: 2021-06-24T15:59:53+01:00
New Revision: c74aea46634347e2ad20111271faebec2da38af3
URL: https://github.com/llvm/llvm-project/commit/c74aea46634347e2ad20111271faebec2da38af3
DIFF: https://github.com/llvm/llvm-project/commit/c74aea46634347e2ad20111271faebec2da38af3.diff
LOG: [AArch64] Precommit extending load tests for D104782. NFC.
Added:
llvm/test/CodeGen/AArch64/neon-extload.ll
llvm/test/CodeGen/AArch64/neon-truncstore.ll
Modified:
Removed:
llvm/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/neon-extload.ll b/llvm/test/CodeGen/AArch64/neon-extload.ll
new file mode 100644
index 0000000000000..321a1babb411d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/neon-extload.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=LE
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=BE
+
+define <4 x i32> @fsext_v4i32(<4 x i8>* %a) {
+; LE-LABEL: fsext_v4i32:
+; LE: // %bb.0:
+; LE-NEXT: ldrsb w8, [x0]
+; LE-NEXT: ldrsb w9, [x0, #1]
+; LE-NEXT: ldrsb w10, [x0, #2]
+; LE-NEXT: ldrsb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.s[1], w9
+; LE-NEXT: mov v0.s[2], w10
+; LE-NEXT: mov v0.s[3], w11
+; LE-NEXT: ret
+;
+; BE-LABEL: fsext_v4i32:
+; BE: // %bb.0:
+; BE-NEXT: ldrsb w8, [x0]
+; BE-NEXT: ldrsb w9, [x0, #1]
+; BE-NEXT: ldrsb w10, [x0, #2]
+; BE-NEXT: ldrsb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.s[1], w9
+; BE-NEXT: mov v0.s[2], w10
+; BE-NEXT: mov v0.s[3], w11
+; BE-NEXT: rev64 v0.4s, v0.4s
+; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = sext <4 x i8> %x to <4 x i32>
+ ret <4 x i32> %y
+}
+
+define <4 x i32> @fzext_v4i32(<4 x i8>* %a) {
+; LE-LABEL: fzext_v4i32:
+; LE: // %bb.0:
+; LE-NEXT: ldrb w8, [x0]
+; LE-NEXT: ldrb w9, [x0, #1]
+; LE-NEXT: ldrb w10, [x0, #2]
+; LE-NEXT: ldrb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.s[1], w9
+; LE-NEXT: mov v0.s[2], w10
+; LE-NEXT: mov v0.s[3], w11
+; LE-NEXT: ret
+;
+; BE-LABEL: fzext_v4i32:
+; BE: // %bb.0:
+; BE-NEXT: ldrb w8, [x0]
+; BE-NEXT: ldrb w9, [x0, #1]
+; BE-NEXT: ldrb w10, [x0, #2]
+; BE-NEXT: ldrb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.s[1], w9
+; BE-NEXT: mov v0.s[2], w10
+; BE-NEXT: mov v0.s[3], w11
+; BE-NEXT: rev64 v0.4s, v0.4s
+; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = zext <4 x i8> %x to <4 x i32>
+ ret <4 x i32> %y
+}
+
+define i32 @loadExt.i32(<4 x i8>* %ref) {
+; CHECK-LABEL: loadExt.i32:
+; CHECK: ldrb
+; LE-LABEL: loadExt.i32:
+; LE: // %bb.0:
+; LE-NEXT: ldrb w0, [x0]
+; LE-NEXT: ret
+;
+; BE-LABEL: loadExt.i32:
+; BE: // %bb.0:
+; BE-NEXT: ldrb w0, [x0]
+; BE-NEXT: ret
+ %a = load <4 x i8>, <4 x i8>* %ref
+ %vecext = extractelement <4 x i8> %a, i32 0
+ %conv = zext i8 %vecext to i32
+ ret i32 %conv
+}
+
+define <4 x i16> @fsext_v4i16(<4 x i8>* %a) {
+; LE-LABEL: fsext_v4i16:
+; LE: // %bb.0:
+; LE-NEXT: ldrsb w8, [x0]
+; LE-NEXT: ldrsb w9, [x0, #1]
+; LE-NEXT: ldrsb w10, [x0, #2]
+; LE-NEXT: ldrsb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.h[1], w9
+; LE-NEXT: mov v0.h[2], w10
+; LE-NEXT: mov v0.h[3], w11
+; LE-NEXT: // kill: def $d0 killed $d0 killed $q0
+; LE-NEXT: ret
+;
+; BE-LABEL: fsext_v4i16:
+; BE: // %bb.0:
+; BE-NEXT: ldrsb w8, [x0]
+; BE-NEXT: ldrsb w9, [x0, #1]
+; BE-NEXT: ldrsb w10, [x0, #2]
+; BE-NEXT: ldrsb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.h[1], w9
+; BE-NEXT: mov v0.h[2], w10
+; BE-NEXT: mov v0.h[3], w11
+; BE-NEXT: rev64 v0.4h, v0.4h
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = sext <4 x i8> %x to <4 x i16>
+ ret <4 x i16> %y
+}
+
+define <4 x i16> @fzext_v4i16(<4 x i8>* %a) {
+; LE-LABEL: fzext_v4i16:
+; LE: // %bb.0:
+; LE-NEXT: ldrb w8, [x0]
+; LE-NEXT: ldrb w9, [x0, #1]
+; LE-NEXT: ldrb w10, [x0, #2]
+; LE-NEXT: ldrb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.h[1], w9
+; LE-NEXT: mov v0.h[2], w10
+; LE-NEXT: mov v0.h[3], w11
+; LE-NEXT: // kill: def $d0 killed $d0 killed $q0
+; LE-NEXT: ret
+;
+; BE-LABEL: fzext_v4i16:
+; BE: // %bb.0:
+; BE-NEXT: ldrb w8, [x0]
+; BE-NEXT: ldrb w9, [x0, #1]
+; BE-NEXT: ldrb w10, [x0, #2]
+; BE-NEXT: ldrb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.h[1], w9
+; BE-NEXT: mov v0.h[2], w10
+; BE-NEXT: mov v0.h[3], w11
+; BE-NEXT: rev64 v0.4h, v0.4h
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = zext <4 x i8> %x to <4 x i16>
+ ret <4 x i16> %y
+}
diff --git a/llvm/test/CodeGen/AArch64/neon-truncStore-extLoad.ll b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
similarity index 66%
rename from llvm/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
rename to llvm/test/CodeGen/AArch64/neon-truncstore.ll
index 2f2f54fd5a5de..2bbab0bfa3e56 100644
--- a/llvm/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
+++ b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
@@ -38,30 +38,3 @@ define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
store <8 x i8> %b, <8 x i8>* %result
ret void
}
-
-; A vector LoadExt can not be selected.
-; Test a vector load IR and a sext/zext IR can be selected correctly.
-define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
-; CHECK-LABEL: loadSExt.v4i8:
-; CHECK: ldrsb
- %a = load <4 x i8>, <4 x i8>* %ref
- %conv = sext <4 x i8> %a to <4 x i32>
- ret <4 x i32> %conv
-}
-
-define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
-; CHECK-LABEL: loadZExt.v4i8:
-; CHECK: ldrb
- %a = load <4 x i8>, <4 x i8>* %ref
- %conv = zext <4 x i8> %a to <4 x i32>
- ret <4 x i32> %conv
-}
-
-define i32 @loadExt.i32(<4 x i8>* %ref) {
-; CHECK-LABEL: loadExt.i32:
-; CHECK: ldrb
- %a = load <4 x i8>, <4 x i8>* %ref
- %vecext = extractelement <4 x i8> %a, i32 0
- %conv = zext i8 %vecext to i32
- ret i32 %conv
-}
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