[PATCH] D104855: [PowerPC] Change VSRpRC allocation order

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, shchenz, jsji, PowerPC.
Herald added subscribers: steven.zhang, kbarton, hiraditya, qcolombet.
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On PowerPC, `VSRpRC` represents the pairs of even and odd VSX register (`(vs0, vs1)`, `(vs2, vs3)`, ...).`VRRC` means the latter 32 registers in `VSRC`. So in some cases, when we're handling incoming `VRRC` arguments with `VSRpRC`, extra copies are produced.

This patch changes the allocation order of `VSRpRC` to put latter 32 ones first. This should not affect ACC/UACC since they only own the first 32 VSX registers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104855

Files:
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
  llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
  llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
  llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
  llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/spill-vec-pair.ll

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