[PATCH] D104832: [TargetLowering][ARM] Don't alter opaque constants in TargetLowering::ShrinkDemandedConstant.

Roger Ferrer Ibanez via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 24 01:48:18 PDT 2021


rogfer01 added a comment.

> The affected ARM test changes because a constant become non-opaque
> and eventually enabled some constant folding. This no longer happens.
> I checked and InstCombine is able to simplify this test. I'm not sure exactly
> what it was trying to test.

Looking at the original diff, back then we only cared about  small subset of it where we checked that some constants were materialised in efficient ways.

   define i1 @t11() {
   entry:
     %bit = alloca i32
     %load = load i32, i32* %bit
     %clear = and i32 %load, -4096
     %set = or i32 %clear, 33
     store i32 %set, i32* %bit
     %load1 = load i32, i32* %bit
     %clear2 = and i32 %load1, -33550337
     %set3 = or i32 %clear2, 40960
     %clear5 = and i32 %set3, 4095
     %rem = srem i32 %clear5, 10
     %clear9 = and i32 %set3, -4096
     %set10 = or i32 %clear9, %rem
     store i32 %set10, i32* %bit
     %clear12 = and i32 %set10, 4095
     %cmp = icmp eq i32 %clear12, 3
     ret i1 %cmp
   
   ; ARM-LABEL: t11:
  -; ARM: mov     r0, #0
  -; ARM: cmp     r1, #3
  -; ARM: moveq   r0, #1
  +; ARM: rsbs r1, r0, #0
  +; ARM: adc  r0, r0, r1
   
   ; ARMT2-LABEL: t11:
  -; ARMT2: mov     r0, #0
  -; ARMT2: cmp     r1, #3
  -; ARMT2: movweq  r0, #1
  +; ARMT2: clz r0, r0
  +; ARMT2: lsr r0, r0, #5
   
   ; THUMB1-LABEL: t11:
   ; THUMB1-NOT: movs r0, #0
   ; THUMB1: movs r0, #5
   
   ; THUMB2-LABEL: t11:
  -; THUMB2: movs    r0, #0
  -; THUMB2: cmp     r1, #3
  -; THUMB2: it      eq
  -; THUMB2: moveq   r0, #1
  +; THUMB2: clz r0, r0
  +; THUMB2: lsrs r0, r0, #5
   }

The thumb checks (ARMT2 and THUMB*) seem still to be there. (The Arm expectation somehow seems to have been gone since 9d2df964070700ae0d244e84572ac2275050e49a <https://reviews.llvm.org/rG9d2df964070700ae0d244e84572ac2275050e49a> in a change that seems positive overall)

When `update_llc_test_check.py` was applied it also included some part of the test that I understand it wasn't originally relevant.

The culprit seems to be a bitcast introduced by `consthoist` but I haven't tried to understand what it is doing to be honest. It looks like it is trying hard to push a constant into a (named) value (perhaps we want the constant materialised at all costs) and bitcast is a hackish way to achieve this?

  *** IR Dump Before Constant Hoisting (consthoist) ***
  define i1 @t11() #0 {
  entry:
    %bit = alloca i32, align 4
    %load = load i32, i32* %bit, align 4
    %clear = and i32 %load, -4096
    %set = or i32 %clear, 33
    store i32 %set, i32* %bit, align 4
    %load1 = load i32, i32* %bit, align 4
    %clear2 = and i32 %load1, -33550337
    %set3 = or i32 %clear2, 40960
    %clear5 = and i32 %set3, 4095
    %rem = srem i32 %clear5, 10
    %clear9 = and i32 %set3, -4096
    %set10 = or i32 %clear9, %rem
    store i32 %set10, i32* %bit, align 4
    %clear12 = and i32 %set10, 4095
    %cmp = icmp eq i32 %clear12, 3
    ret i1 %cmp
  }
  *** IR Dump After Constant Hoisting (consthoist) ***
  define i1 @t11() #0 {
  entry:
    %const1 = bitcast i32 -4096 to i32  ; ---
    %const = bitcast i32 4095 to i32    ; ---
    %bit = alloca i32, align 4
    %load = load i32, i32* %bit, align 4
    %clear = and i32 %load, %const1
    %set = or i32 %clear, 33
    store i32 %set, i32* %bit, align 4
    %load1 = load i32, i32* %bit, align 4
    %clear2 = and i32 %load1, -33550337
    %set3 = or i32 %clear2, 40960
    %clear5 = and i32 %set3, %const
    %rem = srem i32 %clear5, 10
    %clear9 = and i32 %set3, %const1
    %set10 = or i32 %clear9, %rem
    store i32 %set10, i32* %bit, align 4
    %clear12 = and i32 %set10, %const
    %cmp = icmp eq i32 %clear12, 3
    ret i1 %cmp
  }


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104832/new/

https://reviews.llvm.org/D104832



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