[llvm] a37cf17 - [RISCV] Add explicit copy to V0 in the masked vmsge(u).vx intrinsic handling.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-06-23T08:04:42-07:00
New Revision: a37cf17834d39411ed1d669098b428f8374c5b45

URL: https://github.com/llvm/llvm-project/commit/a37cf17834d39411ed1d669098b428f8374c5b45
DIFF: https://github.com/llvm/llvm-project/commit/a37cf17834d39411ed1d669098b428f8374c5b45.diff

LOG: [RISCV] Add explicit copy to V0 in the masked vmsge(u).vx intrinsic handling.

This is consistent with our other masked vector instructions.
Previously we found cases where not doing this broke fast reg
alloc.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e7604c2702e71..9b7f135f45fa9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -687,11 +687,17 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
         return;
       }
 
+      // Mask needs to be copied to V0.
+      SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL,
+                                           RISCV::V0, Mask, SDValue());
+      SDValue Glue = Chain.getValue(1);
+      SDValue V0 = CurDAG->getRegister(RISCV::V0, VT);
+
       // Otherwise use
       // vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
       SDValue Cmp = SDValue(
           CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
-                                 {MaskedOff, Src1, Src2, Mask, VL, SEW}),
+                                 {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}),
           0);
       ReplaceNode(Node, CurDAG->getMachineNode(VMXOROpcode, DL, VT,
                                                {Cmp, Mask, VL, MaskSEW}));