[PATCH] D103614: [PowerPC][AIX] Generate inlined quadword lock free atomic operations via AtomicExpand

[Jinsong Ji via Phabricator via llvm-commits]

jsji added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1545
+  def int_ppc_atomicrmw_umax_i128 : AtomicRMW128Intrinsic;
+  def int_ppc_atomicrmw_umin_i128 : AtomicRMW128Intrinsic;
+}
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lkail wrote:
> efriedma wrote:
> > Adding IR intrinsics for this is a little weird.  Is there any reason you can't just use SelectionDAG custom legalization for these operations?  I mean, not that it doesn't work this way, but it seems more complicated overall.
> Exploit AtomicExpandPass looks easier from my side :). And what's more current PPC backend also has spilling issues with `-O0`(fastregalloc enabled), see https://bugs.llvm.org/show_bug.cgi?id=50780. Maybe we should unify PPC's instruction selection of atomic operations one day (PPC also has partword atomics which is feasible to use MaskedIntrinsic) which I need more feedback from @nemanjai and @jsji .
Yes, I think we should refactor partword atomics to use AtomicExpandPass as well, although not necessary do it now.


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https://reviews.llvm.org/D103614