[PATCH] D104771: [AArch64] Add CodeGen tests for vector reduction intrinsics. NFC

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

Thanks for adding these test. A few nits inlined, but no need for another review if you're happy to make a few changes before committing (but I can always have another look).



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Comment at: llvm/test/CodeGen/AArch64/reduce-or.ll:355
+declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
+declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
+declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
----------------
You may want to add <2 x i32> as that is a common type and supported by the vector instructions.


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Comment at: llvm/test/CodeGen/AArch64/reduce-or.ll:366
+declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
+declare i8 @llvm.vector.reduce.or.v64i8(<64 x i8>)
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I think you can remove this one because the 32 x i8 case above is already testing a type that doesn't fit in a vector register.

The same 2 comments here apply to the other files as well.


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Comment at: llvm/test/CodeGen/AArch64/reduce-xor.ll:4
+
+define i1 @test_redor_v1i1(<1 x i1> %a) {
+; CHECK-LABEL: test_redor_v1i1:
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Nit: `test_redor_v1i1` -> `test_redxor_v1i1`

And a few more below.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D104771/new/

https://reviews.llvm.org/D104771