[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via llvm-commits]

Jim updated this revision to Diff 353655.
Jim added a comment.

1. Address comments about coding style
2. Append postfix `valid` to testcase file name
3. Fix the changes of encoding in version 0.5.3
4. Remove EmitPriority = 2 for rdov and clrov. It would emit no alias `csrr rd, vxsat` and `csrci vxsat, 1` instead.
5. Give a name to sys register vxsat for reference its encoding.
6. Let X0 is a legal operand of even/odd paired-register. Add a dummy register ZERO to pair with X0. I am not sure that is a good implementation by adding a dummy register. X0 paired with X1 is not conformed with the spec.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/rv32zpn-invalid.s
  llvm/test/MC/RISCV/rv32zpsfoperand-invalid.s
  llvm/test/MC/RISCV/rv32zpsfoperand-valid.s
  llvm/test/MC/RISCV/rv64zpn-invalid.s
  llvm/test/MC/RISCV/rv64zprvsfextra-invalid.s
  llvm/test/MC/RISCV/rv64zprvsfextra-valid.s
  llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s
  llvm/test/MC/RISCV/rv64zpsfoperand-valid.s
  llvm/test/MC/RISCV/rvp-non-simd-valid.s
  llvm/test/MC/RISCV/rvp-partial-simd-valid.s
  llvm/test/MC/RISCV/rvp-simd-alu-valid.s
  llvm/test/MC/RISCV/rvp-simd-cmp-valid.s
  llvm/test/MC/RISCV/rvp-simd-misc-valid.s
  llvm/test/MC/RISCV/rvp-simd-mul-valid.s
  llvm/test/MC/RISCV/rvp-simd-shift-valid.s
  llvm/test/MC/RISCV/rvp-simd-unpacking-valid.s

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