[PATCH] D104264: Fix atomic loads and stores of 64-bit values in non-default address spaces on ARM

[David Chisnall via Phabricator via llvm-commits]

theraven added a comment.

The Morello (AArch64 + CHERI) implementation uses AS 200 for capabilities and does different instruction selection for loads and stores (including atomics) depending on the address space.

The back end should never see IR that contains address spaces that don't exist for that back end.  I'd expect that code wanting to use AS1 to indicate GC pointers should rewrite them to AS0 immediately before codegen.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104264/new/

https://reviews.llvm.org/D104264