[PATCH] D104698: [TableGen] Fix printing second PC-relative operand

[Igor Kudrin via Phabricator via llvm-commits]

ikudrin created this revision.
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If an instruction has several operands and a PC-relative one is not the first of them, the generator may produce the code that does not pass the `Address` parameter to the printout method. For example, for an Arm instruction `LE LR, $imm`, it reuses the same code as for other instructions where the second operand is not PC-relative:

  void ARMInstPrinter::printInstruction(...) {
  ...
    case 11:
      // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, ...
      printOperand(MI, 1, STI, O);
      O << ", ";
      printOperand(MI, 2, STI, O);
      break;
  ...

The patch fixes that by considering `PCRel` when comparing `AsmWriterOperand` values.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104698

Files:
  llvm/test/TableGen/AsmWriterPCRelOp.td
  llvm/utils/TableGen/AsmWriterInst.h


Index: llvm/utils/TableGen/AsmWriterInst.h
===================================================================
--- llvm/utils/TableGen/AsmWriterInst.h
+++ llvm/utils/TableGen/AsmWriterInst.h
@@ -66,7 +66,8 @@
     bool operator!=(const AsmWriterOperand &Other) const {
       if (OperandType != Other.OperandType || Str != Other.Str) return true;
       if (OperandType == isMachineInstrOperand)
-        return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
+        return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier ||
+               PCRel != Other.PCRel;
       return false;
     }
     bool operator==(const AsmWriterOperand &Other) const {
Index: llvm/test/TableGen/AsmWriterPCRelOp.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/AsmWriterPCRelOp.td
@@ -0,0 +1,38 @@
+// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s > %t.log
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+}
+
+def R0 : Register<"r0">;
+def Reg : RegisterClass<"Reg", [i32], 0, (add R0)>;
+
+def IntOperand: Operand<i32>;
+
+def PCRelOperand : Operand<i32> {
+  let OperandType = "OPERAND_PCREL";
+}
+
+def foo : Instruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins Reg:$reg, IntOperand:$imm);
+  let AsmString = "foo $reg, $imm";
+}
+
+def bar : Instruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins Reg:$reg, PCRelOperand:$imm);
+  let AsmString = "bar $reg, $imm";
+}
+
+// CHECK:      ArchInstPrinter::printInstruction
+// CHECK:      // bar, foo
+// CHECK-NEXT: printOperand(MI, 0, O);
+// CHECK:      // foo
+// CHECK-NEXT: printOperand(MI, 1, O);
+// CHECK:      // bar
+// CHECK-NEXT: printOperand(MI, Address, 1, O);


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