[PATCH] D103614: [PowerPC][AIX][RFC] Generate inlined quadword lock free atomic operations via AtomicExpand

[Kai Luo via Phabricator via llvm-commits]

lkail updated this revision to Diff 353585.
lkail added reviewers: asb, jyknight.
lkail added a comment.
Herald added a subscriber: mgorny.

Follow @efriedma and @jsji 's suggestions, I adopt the method introduced in https://reviews.llvm.org/D47882, which expand atomic operations post RA to avoid spilling that might prevent LL/SC progress.

Update:

- Add intrinsics in `InstrinsicsPowerPC.td` to lower LLVM IR via AtomicExpandPass's `MaskedIntrinsic` kind.
- Update `PPCInstr64bit.td` to pattern match intrinsics and generate pseudo instructions
- Add post RA pass `ppc-atomic-expand` to expand pseudo instructions

Fixed:

- Uninitialized `PMV.ShiftAmt` in AtomicExpandPass

More atomic operations are being added.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103614/new/

https://reviews.llvm.org/D103614

Files:
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/CodeGen/AtomicExpandPass.cpp
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/atomicrmw-i128.ll

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