[PATCH] D104622: [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/sdiv64.ll:502
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
+; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
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This looks like a minor regression. Why are we still loading s0? Maybe not worth holding up the patch for though.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104622/new/

https://reviews.llvm.org/D104622