[PATCH] D103800: [AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions

Tue Jun 22 01:34:04 PDT 2021

foad accepted this revision.
foad added a comment.
This revision is now accepted and ready to land.

LGTM with the caveat that I don't understand all the implementation details -- in particular anything you could do to explain or simplify the complicated expression in MIMGInstructions.td would be much appreciated!

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Comment at: llvm/lib/Target/AMDGPU/MIMGInstructions.td:765-766
                   !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]),
-                  !if(!or(!eq(dw, 3), !eq(dw, 5)), dw, !add(dw, 1))>,
-                  // we still want _V4/_V8 for codegen with 3/5 dwords
+                  !if(!or(!eq(dw, 3), !eq(dw, 5)), dw,
+                      !if(!or(!eq(dw, 6), !eq(dw, 7)), lhs.Min, !add(dw, 1)))>,
+                  // we still want _V4 for 3 dwords codegen
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I have never understood this bit and I understand it even less now that 6 and 7 are treated differently from 3 and 5.

Repository:
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  https://reviews.llvm.org/D103800/new/

https://reviews.llvm.org/D103800