[PATCH] D103408: Teach peephole optimizer to not emit sub-register defs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/CodeGen/PeepholeOptimizer.cpp:593
+      //
+      if (UseSrcSubIdx && (UseMI->getOpcode() == TargetOpcode::COPY)) {
+        UseSrcSubIdx = false;
----------------
I don't see why you need to special case the use opcode


================
Comment at: llvm/lib/CodeGen/PeepholeOptimizer.cpp:612
                                    TII->get(TargetOpcode::COPY), NewVR)
         .addReg(DstReg, 0, SubIdx);
       // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
----------------
The SubIdx should not be passed through here?


================
Comment at: llvm/test/CodeGen/PowerPC/peephole-subreg.mir:5-30
+--- |
+  declare i64 @strlen() local_unnamed_addr
+
+  define dso_local fastcc void @check_format_info_main() unnamed_addr {
+  entry:
+    %0 = zext i8 undef to i32
+    %cond = icmp eq i32 %0, 0
----------------
IR section is not necessary


================
Comment at: llvm/test/CodeGen/PowerPC/peephole-subreg.mir:32
+---
+name:            check_format_info_main
+alignment:       16
----------------
Should use a relevant name and add a descriptive comment


================
Comment at: llvm/test/CodeGen/PowerPC/peephole-subreg.mir:35-42
+registers:
+  - { id: 0, class: crbitrc }
+  - { id: 1, class: g8rc }
+  - { id: 2, class: g8rc_and_g8rc_nox0 }
+  - { id: 3, class: g8rc }
+  - { id: 4, class: gprc_and_gprc_nor0 }
+  - { id: 5, class: gprc }
----------------
Registers section not necessary


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103408/new/

https://reviews.llvm.org/D103408