[llvm] b663f30 - [RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 19 12:14:55 PDT 2021
Author: Craig Topper
Date: 2021-06-19T12:10:42-07:00
New Revision: b663f30fa45ce86c8a3362624b87ccb372bd036a
URL: https://github.com/llvm/llvm-project/commit/b663f30fa45ce86c8a3362624b87ccb372bd036a
DIFF: https://github.com/llvm/llvm-project/commit/b663f30fa45ce86c8a3362624b87ccb372bd036a.diff
LOG: [RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.
If the outer add has an simm12 immediate operand we should prefer
it instead of materializing it in a register. This would guarantee
and extra instruction and temporary register. Since we don't check
one use on the shl or zext we might generate more instructions if
there is an additional user.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv64zba.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index c43d5bc32c1f..278a83194552 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -963,12 +963,18 @@ def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV32 GPR:$rs)>;
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV64 GPR:$rs)>;
+// Pattern to exclude simm12 immediates from matching.
+def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
+ auto *C = dyn_cast<ConstantSDNode>(N);
+ return !C || !isInt<12>(C->getSExtValue());
+}]>;
+
let Predicates = [HasStdExtZba] in {
-def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), GPR:$rs2),
+def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), non_imm12:$rs2),
(SH1ADD GPR:$rs1, GPR:$rs2)>;
-def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), GPR:$rs2),
+def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), non_imm12:$rs2),
(SH2ADD GPR:$rs1, GPR:$rs2)>;
-def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), GPR:$rs2),
+def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), non_imm12:$rs2),
(SH3ADD GPR:$rs1, GPR:$rs2)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
@@ -996,22 +1002,22 @@ def : Pat<(i64 (SLLIUWPat GPR:$rs1, uimm5:$shamt)),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), GPR:$rs2)),
+def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), non_imm12:$rs2)),
(ADDUW GPR:$rs1, GPR:$rs2)>;
def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADDUW GPR:$rs, X0)>;
-def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 1)), GPR:$rs2)),
+def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 1)), non_imm12:$rs2)),
(SH1ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 2)), GPR:$rs2)),
+def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 2)), non_imm12:$rs2)),
(SH2ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 3)), GPR:$rs2)),
+def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 3)), non_imm12:$rs2)),
(SH3ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (SLLIUWPat GPR:$rs1, (i64 1)), GPR:$rs2)),
+def : Pat<(i64 (add (SLLIUWPat GPR:$rs1, (i64 1)), non_imm12:$rs2)),
(SH1ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (SLLIUWPat GPR:$rs1, (i64 2)), GPR:$rs2)),
+def : Pat<(i64 (add (SLLIUWPat GPR:$rs1, (i64 2)), non_imm12:$rs2)),
(SH2ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (SLLIUWPat GPR:$rs1, (i64 3)), GPR:$rs2)),
+def : Pat<(i64 (add (SLLIUWPat GPR:$rs1, (i64 3)), non_imm12:$rs2)),
(SH3ADDUW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZba, IsRV64]
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index b979f5c74664..8de56c30b439 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -652,3 +652,171 @@ define i64 @mul288(i64 %a) {
%c = mul i64 %a, 288
ret i64 %c
}
+
+define i64 @sh1add_imm(i64 %0) {
+; RV64I-LABEL: sh1add_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: addi a0, a0, 5
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sh1add_imm:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slli a0, a0, 1
+; RV64IB-NEXT: addi a0, a0, 5
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: sh1add_imm:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: slli a0, a0, 1
+; RV64IBA-NEXT: addi a0, a0, 5
+; RV64IBA-NEXT: ret
+ %a = shl i64 %0, 1
+ %b = add i64 %a, 5
+ ret i64 %b
+}
+
+define i64 @sh2add_imm(i64 %0) {
+; RV64I-LABEL: sh2add_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 2
+; RV64I-NEXT: addi a0, a0, -6
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sh2add_imm:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slli a0, a0, 2
+; RV64IB-NEXT: addi a0, a0, -6
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: sh2add_imm:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: slli a0, a0, 2
+; RV64IBA-NEXT: addi a0, a0, -6
+; RV64IBA-NEXT: ret
+ %a = shl i64 %0, 2
+ %b = add i64 %a, -6
+ ret i64 %b
+}
+
+define i64 @sh3add_imm(i64 %0) {
+; RV64I-LABEL: sh3add_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 3
+; RV64I-NEXT: ori a0, a0, 7
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sh3add_imm:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slli a0, a0, 3
+; RV64IB-NEXT: ori a0, a0, 7
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: sh3add_imm:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: slli a0, a0, 3
+; RV64IBA-NEXT: ori a0, a0, 7
+; RV64IBA-NEXT: ret
+ %a = shl i64 %0, 3
+ %b = add i64 %a, 7
+ ret i64 %b
+}
+
+define i64 @sh1adduw_imm(i32 signext %0) {
+; RV64I-LABEL: sh1adduw_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: srli a0, a0, 31
+; RV64I-NEXT: addi a0, a0, 11
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sh1adduw_imm:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slli.uw a0, a0, 1
+; RV64IB-NEXT: addi a0, a0, 11
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: sh1adduw_imm:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: slli.uw a0, a0, 1
+; RV64IBA-NEXT: addi a0, a0, 11
+; RV64IBA-NEXT: ret
+ %a = zext i32 %0 to i64
+ %b = shl i64 %a, 1
+ %c = add i64 %b, 11
+ ret i64 %c
+}
+
+define i64 @sh2adduw_imm(i32 signext %0) {
+; RV64I-LABEL: sh2adduw_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: srli a0, a0, 30
+; RV64I-NEXT: addi a0, a0, -12
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sh2adduw_imm:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slli.uw a0, a0, 2
+; RV64IB-NEXT: addi a0, a0, -12
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: sh2adduw_imm:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: slli.uw a0, a0, 2
+; RV64IBA-NEXT: addi a0, a0, -12
+; RV64IBA-NEXT: ret
+ %a = zext i32 %0 to i64
+ %b = shl i64 %a, 2
+ %c = add i64 %b, -12
+ ret i64 %c
+}
+
+define i64 @sh3adduw_imm(i32 signext %0) {
+; RV64I-LABEL: sh3adduw_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: srli a0, a0, 29
+; RV64I-NEXT: addi a0, a0, 13
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sh3adduw_imm:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slli.uw a0, a0, 3
+; RV64IB-NEXT: addi a0, a0, 13
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: sh3adduw_imm:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: slli.uw a0, a0, 3
+; RV64IBA-NEXT: addi a0, a0, 13
+; RV64IBA-NEXT: ret
+ %a = zext i32 %0 to i64
+ %b = shl i64 %a, 3
+ %c = add i64 %b, 13
+ ret i64 %c
+}
+
+define i64 @adduw_imm(i32 signext %0) nounwind {
+; RV64I-LABEL: adduw_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: addi a0, a0, 5
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: adduw_imm:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: zext.w a0, a0
+; RV64IB-NEXT: addi a0, a0, 5
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: adduw_imm:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: zext.w a0, a0
+; RV64IBA-NEXT: addi a0, a0, 5
+; RV64IBA-NEXT: ret
+ %a = zext i32 %0 to i64
+ %b = add i64 %a, 5
+ ret i64 %b
+}
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