[llvm] 18dbe68 - [ARM][NFC] Tidy up subtarget frame pointer routines
Tomas Matheson via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 19 09:01:06 PDT 2021
Author: Tomas Matheson
Date: 2021-06-19T17:00:45+01:00
New Revision: 18dbe6897857944653ee8f68dca8d63bc38aaff8
URL: https://github.com/llvm/llvm-project/commit/18dbe6897857944653ee8f68dca8d63bc38aaff8
DIFF: https://github.com/llvm/llvm-project/commit/18dbe6897857944653ee8f68dca8d63bc38aaff8.diff
LOG: [ARM][NFC] Tidy up subtarget frame pointer routines
getFramePointerReg only depends on information in ARMSubtarget,
so move it in there so it can be accessed from more places.
Make use of ARMSubtarget::getFramePointerReg to remove duplicated code.
The main use of useR7AsFramePointer is getFramePointerReg, so inline it.
Differential Revision: https://reviews.llvm.org/D104476
Added:
Modified:
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 04e21867d5711..ba594b7f09357 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1293,7 +1293,6 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
const MachineFunction &MF = *MI->getParent()->getParent();
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
- unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
// If we just ended a constant pool, mark it as such.
if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
@@ -2039,12 +2038,12 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
if (STI.isTargetDarwin() || STI.isTargetWindows()) {
// These platforms always use the same frame register
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
- .addReg(FramePtr)
- .addReg(SrcReg)
- .addImm(0)
- // Predicate.
- .addImm(ARMCC::AL)
- .addReg(0));
+ .addReg(STI.getFramePointerReg())
+ .addReg(SrcReg)
+ .addImm(0)
+ // Predicate.
+ .addImm(ARMCC::AL)
+ .addReg(0));
} else {
// If the calling code might use either R7 or R11 as
// frame pointer register, restore it into both.
@@ -2109,12 +2108,12 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
if (STI.isTargetDarwin() || STI.isTargetWindows()) {
// These platforms always use the same frame register
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
- .addReg(FramePtr)
- .addReg(SrcReg)
- .addImm(0)
- // Predicate.
- .addImm(ARMCC::AL)
- .addReg(0));
+ .addReg(STI.getFramePointerReg())
+ .addReg(SrcReg)
+ .addImm(0)
+ // Predicate.
+ .addImm(ARMCC::AL)
+ .addReg(0));
} else {
// If the calling code might use either R7 or R11 as
// frame pointer register, restore it into both.
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 2f7f3eee98442..4883e5693f87d 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -59,10 +59,6 @@ ARMBaseRegisterInfo::ARMBaseRegisterInfo()
ARM_MC::initLLVMToCVRegMapping(this);
}
-static unsigned getFramePointerReg(const ARMSubtarget &STI) {
- return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
-}
-
const MCPhysReg*
ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
@@ -206,7 +202,7 @@ getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, ARM::FPSCR);
markSuperRegs(Reserved, ARM::APSR_NZCV);
if (TFI->hasFP(MF))
- markSuperRegs(Reserved, getFramePointerReg(STI));
+ markSuperRegs(Reserved, STI.getFramePointerReg());
if (hasBasePointer(MF))
markSuperRegs(Reserved, BasePtr);
// Some targets reserve R9.
@@ -243,7 +239,7 @@ bool ARMBaseRegisterInfo::isInlineAsmReadOnlyReg(const MachineFunction &MF,
BitVector Reserved(getNumRegs());
markSuperRegs(Reserved, ARM::PC);
if (TFI->hasFP(MF))
- markSuperRegs(Reserved, getFramePointerReg(STI));
+ markSuperRegs(Reserved, STI.getFramePointerReg());
if (hasBasePointer(MF))
markSuperRegs(Reserved, BasePtr);
assert(checkAllSuperRegsMarked(Reserved));
@@ -444,6 +440,7 @@ bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
const MachineRegisterInfo *MRI = &MF.getRegInfo();
const ARMFrameLowering *TFI = getFrameLowering(MF);
+ const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
// We can't realign the stack if:
// 1. Dynamic stack realignment is explicitly disabled,
// 2. There are VLAs in the function and the base pointer is disabled.
@@ -451,7 +448,7 @@ bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
return false;
// Stack realignment requires a frame pointer. If we already started
// register allocation with frame pointer elimination, it is too late now.
- if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
+ if (!MRI->canReserveReg(STI.getFramePointerReg()))
return false;
// We may also need a base pointer if there are dynamic allocas or stack
// pointer adjustments around calls.
@@ -477,7 +474,7 @@ ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const ARMFrameLowering *TFI = getFrameLowering(MF);
if (TFI->hasFP(MF))
- return getFramePointerReg(STI);
+ return STI.getFramePointerReg();
return ARM::SP;
}
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index c115cc1e413dc..42a99d7b48434 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -94,7 +94,7 @@
// or stores.
//
// The frame pointer might be chosen to be r7 or r11, depending on the target
-// architecture and operating system. See ARMSubtarget::useR7AsFramePointer for
+// architecture and operating system. See ARMSubtarget::getFramePointerReg for
// details.
//
// Outgoing function arguments must be at the bottom of the stack frame when
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 4740af87d4971..a8a9ae66b4abd 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -820,8 +820,10 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
}
- bool useR7AsFramePointer() const {
- return isTargetDarwin() || (!isTargetWindows() && isThumb());
+ MCPhysReg getFramePointerReg() const {
+ if (isTargetDarwin() || (!isTargetWindows() && isThumb()))
+ return ARM::R7;
+ return ARM::R11;
}
/// Returns true if the frame setup is split into two separate pushes (first
@@ -829,7 +831,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
/// to lr. This is always required on Thumb1-only targets, as the push and
/// pop instructions can't access the high registers.
bool splitFramePushPop(const MachineFunction &MF) const {
- return (useR7AsFramePointer() &&
+ return (getFramePointerReg() == ARM::R7 &&
MF.getTarget().Options.DisableFramePointerElim(MF)) ||
isThumb1Only();
}
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index 003f6e5e17896..ccd272a8617d7 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -681,7 +681,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
// R7 may be used as a frame pointer, hence marked as not generally
// allocatable, however there's no reason to not use it as a temporary for
// restoring LR.
- if (STI.useR7AsFramePointer())
+ if (STI.getFramePointerReg() == ARM::R7)
PopFriendly.set(ARM::R7);
assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
More information about the llvm-commits
mailing list