[llvm] d934b72 - [RISCV] Optimize add-mul in the zba extension with SH*ADD
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 18 23:57:16 PDT 2021
Author: Ben Shi
Date: 2021-06-19T14:33:27+08:00
New Revision: d934b72809cb3cbc9f646a2b505e781e0b8b3d7b
URL: https://github.com/llvm/llvm-project/commit/d934b72809cb3cbc9f646a2b505e781e0b8b3d7b
DIFF: https://github.com/llvm/llvm-project/commit/d934b72809cb3cbc9f646a2b505e781e0b8b3d7b.diff
LOG: [RISCV] Optimize add-mul in the zba extension with SH*ADD
This patch does the following optimization.
Rx + Ry * 18 => (SH1ADD (SH3ADD Rx, Rx), Ry)
Rx + Ry * 20 => (SH2ADD (SH2ADD Rx, Rx), Ry)
Rx + Ry * 24 => (SH3ADD (SH1ADD Rx, Rx), Ry)
Rx + Ry * 36 => (SH2ADD (SH3ADD Rx, Rx), Ry)
Rx + Ry * 40 => (SH3ADD (SH2ADD Rx, Rx), Ry)
Rx + Ry * 72 => (SH3ADD (SH3ADD Rx, Rx), Ry)
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D104588
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32zba.ll
llvm/test/CodeGen/RISCV/rv64zba.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index c210caf7fcbe..1c1277426385 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -896,6 +896,10 @@ def add_oneuse : PatFrag<(ops node:$A, node:$B), (add node:$A, node:$B), [{
return N->hasOneUse();
}]>;
+def mul_oneuse : PatFrag<(ops node:$A, node:$B), (mul node:$A, node:$B), [{
+ return N->hasOneUse();
+}]>;
+
/// Simple arithmetic operations
def : PatGprGpr<add, ADD>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 4e52fb8d0cc2..c43d5bc32c1f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -970,6 +970,25 @@ def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), GPR:$rs2),
(SH2ADD GPR:$rs1, GPR:$rs2)>;
def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), GPR:$rs2),
(SH3ADD GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
+ (SH1ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2),
+ (SH1ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2),
+ (SH1ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2),
+ (SH2ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2),
+ (SH2ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
+ (SH2ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
+ (SH3ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
+ (SH3ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
+ (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
} // Predicates = [HasStdExtZba]
let Predicates = [HasStdExtZba, IsRV64] in {
diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll
index 9f114467e40a..7a91f7b5ff59 100644
--- a/llvm/test/CodeGen/RISCV/rv32zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -91,16 +91,14 @@ define i32 @addmul6(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul6:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 6
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh1add a0, a0, a0
+; RV32IB-NEXT: sh1add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul6:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 6
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh1add a0, a0, a0
+; RV32IBA-NEXT: sh1add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 6
%d = add i32 %c, %b
@@ -117,16 +115,14 @@ define i32 @addmul10(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul10:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 10
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh2add a0, a0, a0
+; RV32IB-NEXT: sh1add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul10:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 10
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh2add a0, a0, a0
+; RV32IBA-NEXT: sh1add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 10
%d = add i32 %c, %b
@@ -143,16 +139,14 @@ define i32 @addmul12(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul12:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 12
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh1add a0, a0, a0
+; RV32IB-NEXT: sh2add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul12:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 12
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh1add a0, a0, a0
+; RV32IBA-NEXT: sh2add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 12
%d = add i32 %c, %b
@@ -169,16 +163,14 @@ define i32 @addmul18(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul18:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 18
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh3add a0, a0, a0
+; RV32IB-NEXT: sh1add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul18:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 18
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh3add a0, a0, a0
+; RV32IBA-NEXT: sh1add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 18
%d = add i32 %c, %b
@@ -195,16 +187,14 @@ define i32 @addmul20(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul20:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 20
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh2add a0, a0, a0
+; RV32IB-NEXT: sh2add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul20:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 20
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh2add a0, a0, a0
+; RV32IBA-NEXT: sh2add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 20
%d = add i32 %c, %b
@@ -221,16 +211,14 @@ define i32 @addmul24(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul24:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 24
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh1add a0, a0, a0
+; RV32IB-NEXT: sh3add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul24:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 24
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh1add a0, a0, a0
+; RV32IBA-NEXT: sh3add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 24
%d = add i32 %c, %b
@@ -247,16 +235,14 @@ define i32 @addmul36(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul36:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 36
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh3add a0, a0, a0
+; RV32IB-NEXT: sh2add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul36:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 36
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh3add a0, a0, a0
+; RV32IBA-NEXT: sh2add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 36
%d = add i32 %c, %b
@@ -273,16 +259,14 @@ define i32 @addmul40(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul40:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 40
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh2add a0, a0, a0
+; RV32IB-NEXT: sh3add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul40:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 40
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh2add a0, a0, a0
+; RV32IBA-NEXT: sh3add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 40
%d = add i32 %c, %b
@@ -299,16 +283,14 @@ define i32 @addmul72(i32 %a, i32 %b) {
;
; RV32IB-LABEL: addmul72:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a2, zero, 72
-; RV32IB-NEXT: mul a0, a0, a2
-; RV32IB-NEXT: add a0, a0, a1
+; RV32IB-NEXT: sh3add a0, a0, a0
+; RV32IB-NEXT: sh3add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul72:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a2, zero, 72
-; RV32IBA-NEXT: mul a0, a0, a2
-; RV32IBA-NEXT: add a0, a0, a1
+; RV32IBA-NEXT: sh3add a0, a0, a0
+; RV32IBA-NEXT: sh3add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 72
%d = add i32 %c, %b
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index 153a5492d4f2..b979f5c74664 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -381,16 +381,14 @@ define i64 @addmul6(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul6:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 6
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh1add a0, a0, a0
+; RV64IB-NEXT: sh1add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul6:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 6
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh1add a0, a0, a0
+; RV64IBA-NEXT: sh1add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 6
%d = add i64 %c, %b
@@ -407,16 +405,14 @@ define i64 @addmul10(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul10:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 10
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh2add a0, a0, a0
+; RV64IB-NEXT: sh1add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul10:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 10
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh2add a0, a0, a0
+; RV64IBA-NEXT: sh1add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 10
%d = add i64 %c, %b
@@ -433,16 +429,14 @@ define i64 @addmul12(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul12:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 12
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh1add a0, a0, a0
+; RV64IB-NEXT: sh2add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul12:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 12
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh1add a0, a0, a0
+; RV64IBA-NEXT: sh2add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 12
%d = add i64 %c, %b
@@ -459,16 +453,14 @@ define i64 @addmul18(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul18:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 18
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh3add a0, a0, a0
+; RV64IB-NEXT: sh1add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul18:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 18
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh3add a0, a0, a0
+; RV64IBA-NEXT: sh1add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 18
%d = add i64 %c, %b
@@ -485,16 +477,14 @@ define i64 @addmul20(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul20:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 20
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh2add a0, a0, a0
+; RV64IB-NEXT: sh2add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul20:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 20
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh2add a0, a0, a0
+; RV64IBA-NEXT: sh2add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 20
%d = add i64 %c, %b
@@ -511,16 +501,14 @@ define i64 @addmul24(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul24:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 24
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh1add a0, a0, a0
+; RV64IB-NEXT: sh3add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul24:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 24
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh1add a0, a0, a0
+; RV64IBA-NEXT: sh3add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 24
%d = add i64 %c, %b
@@ -537,16 +525,14 @@ define i64 @addmul36(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul36:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 36
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh3add a0, a0, a0
+; RV64IB-NEXT: sh2add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul36:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 36
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh3add a0, a0, a0
+; RV64IBA-NEXT: sh2add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 36
%d = add i64 %c, %b
@@ -563,16 +549,14 @@ define i64 @addmul40(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul40:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 40
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh2add a0, a0, a0
+; RV64IB-NEXT: sh3add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul40:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 40
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh2add a0, a0, a0
+; RV64IBA-NEXT: sh3add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 40
%d = add i64 %c, %b
@@ -589,16 +573,14 @@ define i64 @addmul72(i64 %a, i64 %b) {
;
; RV64IB-LABEL: addmul72:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a2, zero, 72
-; RV64IB-NEXT: mul a0, a0, a2
-; RV64IB-NEXT: add a0, a0, a1
+; RV64IB-NEXT: sh3add a0, a0, a0
+; RV64IB-NEXT: sh3add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul72:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a2, zero, 72
-; RV64IBA-NEXT: mul a0, a0, a2
-; RV64IBA-NEXT: add a0, a0, a1
+; RV64IBA-NEXT: sh3add a0, a0, a0
+; RV64IBA-NEXT: sh3add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 72
%d = add i64 %c, %b
More information about the llvm-commits
mailing list