[PATCH] D104575: AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
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These used to consistently be zeroed pre-gfx9, but gfx9 made the
situation complicated since now some still do and some don't. This
also manages to pick up a few cases that the pattern fails to optimize
away.

      

We handle some cases with instruction patterns, but some get
through. In particular this improves the integer cases.


https://reviews.llvm.org/D104575

Files:
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/test/CodeGen/AMDGPU/fmax3.ll
  llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
  llvm/test/CodeGen/AMDGPU/fmin3.ll
  llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
  llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
  llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
  llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
  llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
  llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
  llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
  llvm/test/CodeGen/AMDGPU/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/usubsat.ll

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