[PATCH] D102766: [SelectionDAG] Implement PromoteIntRes_INSERT_SUBVECTOR

[Joe Ellis via Phabricator via llvm-commits]

joechrisellis added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:4731
+  SDValue ScaledIdx = DAG.getVScale(
+      dl, StackPtrVT, IdxAPInt.sextOrSelf(StackPtrVT.getSizeInBits()));
+
----------------
peterwaller-arm wrote:
> Thinking: If IdxAPInt is zero, you could set ScaledIdx = Idx. Alternatively, just update Idx if non-zero. This would get rid of some `rdvl ..., #0`.
Good shout -- that's removed a few instructions from the test cases.


================
Comment at: llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll:24
+; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
+  %vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
----------------
peterwaller-arm wrote:
> There is a bit of extraneous stuff going on in these tests, if you choose a couple of optimization passes are you able to shrink them a bit? I'm looking at the store of x29 and extra addpl.
`-O3` doesn't change the lowering here, so I am not sure if these test cases can be reduced by using different flags.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102766/new/

https://reviews.llvm.org/D102766