[PATCH] D104236: [AArch64] Add a TableGen pattern to generate uaddlv from uaddlp and addv

Fri Jun 18 08:45:42 PDT 2021

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. LGTM if you fix the v2i32 pattern to be like the others.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5674
+            (i64 0))), (i64 0))),
+          (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
+           (UADDLVv4i16v V64:$op), ssub), ssub)>;
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v4i16 -> v2i32 here?

But I think the pattern may work without the vector_extract / insert_subvector, just like the v4i32 and v2i64 patterns do. Then it is overall a bit simpler.

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Comment at: llvm/test/CodeGen/AArch64/neon-uaddlv.ll:23
+; CHECK-NEXT:    ret
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
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There are a lot of spaces here. Can you cut them down to 2, as would be more common :)

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  https://reviews.llvm.org/D104236/new/

https://reviews.llvm.org/D104236