[llvm] 7353bed - [DAG] SelectionDAG::computeKnownBits - use APInt::insertBits to merge subvector knownbits. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-06-18T14:59:01+01:00
New Revision: 7353beda4aa13187d1c9ba03015589272b157c61

URL: https://github.com/llvm/llvm-project/commit/7353beda4aa13187d1c9ba03015589272b157c61
DIFF: https://github.com/llvm/llvm-project/commit/7353beda4aa13187d1c9ba03015589272b157c61.diff

LOG: [DAG] SelectionDAG::computeKnownBits - use APInt::insertBits to merge subvector knownbits. NFCI.

As noticed on D104472 we can use APInt::insertBits which will avoid a lot of temporary APInt creations

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6d2827e85742d..c7f22dd3627f8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2955,8 +2955,8 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
         Known2 = computeKnownBits(N0, SubDemandedElts.shl(i),
                          Depth + 1);
         unsigned Shifts = IsLE ? i : SubScale - 1 - i;
-        Known.One |= Known2.One.zext(BitWidth).shl(SubBitWidth * Shifts);
-        Known.Zero |= Known2.Zero.zext(BitWidth).shl(SubBitWidth * Shifts);
+        Known.One.insertBits(Known2.One, SubBitWidth * Shifts);
+        Known.Zero.insertBits(Known2.Zero, SubBitWidth * Shifts);
       }
     }