[PATCH] D104236: [AArch64] Add a TableGen pattern to generate uaddlv from uaddlp and addv

JinGu Kang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 18 03:36:24 PDT 2021


jaykang10 added a comment.

In D104236#2826609 <https://reviews.llvm.org/D104236#2826609>, @dmgreen wrote:

>> For addp(addlp(x)) ->addv(x), addv genereates i32 output from v4i32 input and i16 output from v4i16 input. However, addp(addlp(x)) generates i64 output from v4i32 input and i32 output from v4i16 input. I think the outputs could not be same with big numbers input between addp(addlp(x)) and addv(x). If I missed something, please let me know.
>
> With types and full opcode names it would be `(i64 addp(v2i64 uaddlp(v4i32 x))) -> (i64 uaddlv(v4i32 x))` or  `(i32 addp(v2i32 uaddlp(v4i16 x))) -> (i32 uaddlv(v4i16 x))`
>
> Do you have an example of where you don't think that would work the same?

Ah, sorry. If it is uaddlv rather than addv, it is ok. Let me try to add it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104236/new/

https://reviews.llvm.org/D104236



More information about the llvm-commits mailing list