[PATCH] D91921: [ARM] Introduce MVETRUNC ISel lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 352950.
dmgreen edited the summary of this revision.
dmgreen added a comment.

Sorry about the very long delay. Other things came up, but I still think this is worthwhile. It feels a little odd to introduce a target node that isn't legal, but it helps in the lowering of truncates under MVE. It should allow us to, instead of expanding the trunc into a lot of lane extract/insert operations, lower them to two truncating stack stores and a reload (which I will do as a separate patch). We can then do the same for zext/sext, which should help improve the worst case lowering for a lot of zext/sext/trunc we currently see. And help with the lowering of nodes like VABD like we see here, and things like VMULL and certain vector reductions.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91921/new/

https://reviews.llvm.org/D91921

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vabdus.ll

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