[PATCH] D104163: [RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:491
+
+  // The choice of VMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally
+  // commutable.
----------------
Comment here needs updating for the right opcodes


================
Comment at: llvm/test/CodeGen/RISCV/rvv/stepvector.ll:492
+; CHECK-NEXT:    vmacc.vx v16, a0, v8
+; CHECK-NEXT:    vmul.vx v8, v8, a0
 ; CHECK-NEXT:    ret
----------------
Seems like this test is regressing. Is there a one-use check that may help here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104163/new/

https://reviews.llvm.org/D104163