[PATCH] D104503: [SCEV] Don't require dominance ordering of add/mul/min/max expressions

[Max Kazantsev via Phabricator via llvm-commits]

mkazantsev added a comment.

I'm pretty sure if you try to give an expression where arguments don't dominate one another to SCEV Expander, it should break.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D104503/new/

https://reviews.llvm.org/D104503